/****************************************************************************
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
    |F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+

    FILE            apb_if.sv

    DESCRIPTION     apb interface

 ****************************************************************************/

`ifndef APB_IF_SV
`define APB_IF_SV

/**
 * Interface: apb_if
 */
interface apb_if (input logic pclk, input logic presetn);

    parameter ADDR_WIDTH  = 32;    // up to 32 bits
    parameter RDATA_WIDTH = 32;    // up to 32 bits
    parameter WDATA_WIDTH = 32;    // up to 32 bits
    parameter SLV_NUM = 15;

    // source is master
    logic [ADDR_WIDTH - 1 : 0]  paddr;   // the APB address bus
    logic [SLV_NUM - 1 : 0]     psel;    // select; the slave device is selected
                                         // and that a data transfer is required
    logic                       penable; // enable; the second and subsequent
                                         // cycles of an APB transfer
    logic                       pwrite;  // direction
    logic [WDATA_WIDTH - 1 : 0] pwdata;  // write data
    
    // source is slave
    logic                       pready;  // ready; the slave uses this signal to
                                         // extend an APB transfer
    logic [RDATA_WIDTH - 1 : 0] prdata;  // read data
    logic                       pslverr; // indicates a transfer failure
    
    // control
    bit has_checks = 1;
    bit has_coverage = 1;
    
    // TODO : coverage and assertions go here...

endinterface : apb_if

`endif
