/****************************************************************************
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
    |F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+

    FILE            reset_seq.sv

    DESCRIPTION     sequence for assertion reset

 ****************************************************************************/

`ifndef RESET_SEQ_SV
`define RESET_SEQ_SV

/**
 * Class: reset_seq
 */
class reset_seq extends reset_base_seq;
    
    // delay before asserting reset (#clk cycles)
    rand int unsigned transmit_del;
    // duration of reset (#clk cycles)
    rand int unsigned duration_time;    
    
    // UVM factory registration
    `uvm_object_utils(reset_seq)
    
    // constraints
    constraint c_transmit_delay { transmit_del <= 10; }
    constraint c_duration_time { duration_time inside {[1:5]}; }

    // new - constructor
    function new(string name = "reset_seq");
        super.new(name);
    endfunction : new
    
    // sequence generation logic in body
    virtual task body();
        // send one transaction
        `uvm_do_with(req, { req.duration == duration_time;
                            req.transmit_delay == transmit_del; } )         
    endtask : body
    
endclass : reset_seq

`endif

