/****************************************************************************
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
    |F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+

    FILE            apb_master_read_all_seq.sv

    DESCRIPTION     sequence for reading from all valid addresses

 ****************************************************************************/

`ifndef APB_MASTER_READ_ALL_SEQ_SV
`define APB_MASTER_READ_ALL_SEQ_SV
    
/**
 * Class: apb_master_read_all_seq
 */
class apb_master_read_all_seq extends apb_master_base_seq;

    // UVM factory registration
    `uvm_object_utils(apb_master_read_all_seq)

    // new - constructor
    function new(string name = "apb_master_read_all_seq");
        super.new(name);
    endfunction : new

    // sequence generation logic in body
    virtual task body();
        bit [ADDR_WIDTH - 1 : 0] end_addr, curr_addr;
        
        // read from all addresses in all slaves
        foreach (p_sequencer.cfg.slave_cfg_queue[i]) begin
            curr_addr = p_sequencer.cfg.slave_cfg_queue[i].start_address;
            end_addr  = p_sequencer.cfg.slave_cfg_queue[i].end_address;
            while (curr_addr != end_addr) begin
                `uvm_do_with(   req, {
                                req.addr == curr_addr;
                                req.dir  == APB_READ;})
                curr_addr++;
            end
            
        end
        
    endtask : body
    
endclass : apb_master_read_all_seq

`endif

