68 lines
1.7 KiB
Systemverilog
68 lines
1.7 KiB
Systemverilog
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_test_top.sv
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DESCRIPTION top module
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- connects DUT and interface
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- generates clk and reset
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- runs UVM test
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****************************************************************************/
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`ifndef I2C_TEST_TOP_SV
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`define I2C_TEST_TOP_SV
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/**
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* Module: i2c_test_top
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*/
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module i2c_test_top;
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import uvm_pkg::*; // import the UVM library
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`include "uvm_macros.svh" // Include the UVM macros
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import i2c_pkg::*; // import the i2c pkg
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`include "i2c_test_lib.sv"
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`include "dut.sv"
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logic clock;
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logic reset;
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// interface
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i2c_if i2c_vif(clock, reset);
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// DUT
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dut #( .ADDR_WIDTH(7),
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.DATA_WIDTH(8)
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) dut_inst (
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.clk (clock),
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.rst (reset),
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.scl (i2c_vif.scl),
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.sda (i2c_vif.sda)
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);
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// set interface in db; run UVM test
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initial begin
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uvm_config_db#(virtual i2c_if)::set(null,"uvm_test_top.*","i2c_if", i2c_vif);
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run_test();
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end
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// initialize clock and reset
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initial begin
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clock <= 1'b0;
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reset <= 1'b1;
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#50 reset <= 1'b0;
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end
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// generate clock
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always #5 clock = ~clock;
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endmodule : i2c_test_top
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`endif
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