73 lines
2.4 KiB
Systemverilog
73 lines
2.4 KiB
Systemverilog
|
/****************************************************************************
|
||
|
|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||
|
|
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||
|
|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||
|
|
|
||
|
|
FILE reset_agent.sv
|
||
|
|
|
||
|
|
DESCRIPTION
|
||
|
|
|
||
|
|
****************************************************************************/
|
||
|
|
|
||
|
|
`ifndef RESET_AGENT_SV
|
||
|
|
`define RESET_AGENT_SV
|
||
|
|
|
||
|
|
// reset sequencer
|
||
|
|
typedef uvm_sequencer#(reset_transaction) reset_sequencer;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Class: reset_agent
|
||
|
|
*/
|
||
|
|
class reset_agent extends uvm_agent;
|
||
|
|
|
||
|
|
// configuration object
|
||
|
|
reset_config cfg;
|
||
|
|
|
||
|
|
// components
|
||
|
|
reset_sequencer seqr;
|
||
|
|
reset_driver drv;
|
||
|
|
reset_monitor mon;
|
||
|
|
|
||
|
|
// UVM factory registration
|
||
|
|
`uvm_component_utils_begin(reset_agent)
|
||
|
|
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)
|
||
|
|
`uvm_component_utils_end
|
||
|
|
|
||
|
|
// new - constructor
|
||
|
|
function new (string name = "reset_agent", uvm_component parent = null);
|
||
|
|
super.new(name, parent);
|
||
|
|
endfunction : new
|
||
|
|
|
||
|
|
// UVM build_phase
|
||
|
|
function void build_phase(uvm_phase phase);
|
||
|
|
super.build_phase(phase);
|
||
|
|
|
||
|
|
// get configuration object from db
|
||
|
|
if(!uvm_config_db#(reset_config)::get(this, "", "reset_config", cfg)) begin
|
||
|
|
`uvm_info("NOCONFIG", "Using default reset_config", UVM_LOW)
|
||
|
|
cfg = reset_config::type_id::create("cfg");
|
||
|
|
uvm_config_db#(reset_config)::set(this, "*", "reset_config", cfg);
|
||
|
|
end
|
||
|
|
|
||
|
|
// create driver and sequencer if agent is active
|
||
|
|
if(cfg.is_active == UVM_ACTIVE) begin
|
||
|
|
seqr = reset_sequencer::type_id::create("seqr", this);
|
||
|
|
drv = reset_driver::type_id::create("drv", this);
|
||
|
|
end
|
||
|
|
// always create monitor
|
||
|
|
mon = reset_monitor::type_id::create("mon", this);
|
||
|
|
endfunction : build_phase
|
||
|
|
|
||
|
|
// UVM connect_phase
|
||
|
|
function void connect_phase(uvm_phase phase);
|
||
|
|
super.connect_phase(phase);
|
||
|
|
// connect driver and sequencer if agent is active
|
||
|
|
if(cfg.is_active == UVM_ACTIVE) begin
|
||
|
|
drv.seq_item_port.connect(seqr.seq_item_export);
|
||
|
|
end
|
||
|
|
endfunction : connect_phase
|
||
|
|
|
||
|
|
endclass : reset_agent
|
||
|
|
|
||
|
|
`endif
|