94 lines
3.1 KiB
Systemverilog
94 lines
3.1 KiB
Systemverilog
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_driver.sv
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DESCRIPTION drives reset
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****************************************************************************/
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`ifndef RESET_DRIVER_SV
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`define RESET_DRIVER_SV
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/**
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* Class: reset_driver
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*/
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class reset_driver extends uvm_driver #(reset_transaction);
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// reset virtual interface
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virtual reset_if vif;
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// configuration
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reset_config cfg;
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// UVM factory registration
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`uvm_component_utils_begin(reset_driver)
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`uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
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`uvm_component_utils_end
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// new - constructor
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function new (string name = "reset_driver", uvm_component parent = null);
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super.new(name, parent);
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endfunction : new
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// UVM build_phase
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virtual function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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// get configuration object from db
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if(!uvm_config_db#(reset_config)::get(this, "*", "reset_config", cfg))
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`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
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endfunction: build_phase
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// UVM connect_phase
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virtual function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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// get interface from db
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if(!uvm_config_db#(virtual reset_if)::get(this, "", "reset_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
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endfunction : connect_phase
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// additional class methods
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extern virtual task run_phase(uvm_phase phase);
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extern virtual function void start_of_simulation_phase(uvm_phase phase);
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extern virtual task drive_tr (reset_transaction tr);
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endclass : reset_driver
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// UVM start_of_simulation_phase
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function void reset_driver::start_of_simulation_phase(uvm_phase phase);
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super.start_of_simulation_phase(phase);
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vif.reset <= cfg.value_at_0; // init reset
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endfunction
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// UVM run_phase
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task reset_driver::run_phase(uvm_phase phase);
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forever begin
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seq_item_port.get_next_item(req);
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drive_tr(req);
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seq_item_port.item_done();
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end
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endtask : run_phase
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// Drives a transfer when an item is ready to be sent.
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task reset_driver::drive_tr (reset_transaction tr);
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`uvm_info( get_type_name(),
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$sformatf("Driving reset: delay %0d clocks duration of %0d clocks",
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tr.transmit_delay, tr.duration),
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UVM_LOW)
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// delay
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if (tr.transmit_delay > 0) begin
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repeat(tr.transmit_delay) @(posedge vif.clk);
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end
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// start reset
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vif.reset <= cfg.active_high;
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// duration
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repeat(tr.duration) @(posedge vif.clk);
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// drop reset
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vif.reset <= ~cfg.active_high;
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endtask : drive_tr
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`endif
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