42 lines
1.3 KiB
Systemverilog
42 lines
1.3 KiB
Systemverilog
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_transaction.sv
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DESCRIPTION reset sequence item
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****************************************************************************/
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`ifndef RESET_TRANSACTION_SV
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`define RESET_TRANSACTION_SV
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/**
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* Class: reset_transaction
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*/
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class reset_transaction extends uvm_sequence_item;
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// delay before asserting reset (#clk cycles)
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rand int unsigned transmit_delay;
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// duration of reset (#clk cycles)
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rand int unsigned duration;
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// constraints
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constraint c_transmit_delay { transmit_delay <= 10; }
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constraint c_duration { duration inside {[0:5]}; }
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// UVM factory registration
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`uvm_object_utils_begin(reset_transaction)
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`uvm_field_int(transmit_delay, UVM_DEFAULT)
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`uvm_field_int(duration, UVM_DEFAULT)
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`uvm_object_utils_end
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// new - constructor
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function new (string name = "reset_transaction");
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super.new(name);
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endfunction : new
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endclass : reset_transaction
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`endif
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