27 lines
410 B
Systemverilog
27 lines
410 B
Systemverilog
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module counter
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(input clk,
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input rst,
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input ce_i,
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input up_i,
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output logic [3:0] q_o);
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logic [3:0] count;
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always_ff @(posedge clk) begin
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if (rst) begin
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count <= 4'b0000;
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end
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else if(ce_i) begin
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if(up_i) begin
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count <= count + 1'b1;
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end
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else begin
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count <= count - 1'b1;
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end
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end
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end
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assign q_o = count;
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endmodule : counter
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