48 lines
906 B
Systemverilog
48 lines
906 B
Systemverilog
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module simple_tb;
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logic clk;
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logic rst;
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logic ce;
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logic up;
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logic [3 : 0] data;
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counter cnt_inst (clk, rst, ce, up, data);
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function void compare_values(logic [3:0] expected, logic [3 : 0] received);
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if(expected !== received) begin
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$error("Error in comparison: expected %0h, received %0h\n", expected, received);
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end
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else begin
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$display("Successful comparison at time %0t with value %0h", $time, expected);
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end
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endfunction : compare_values
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initial begin
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$display("Starting simulation...");
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#500ns;
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$finish;
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end
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initial begin
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repeat(3) @(posedge clk iff !rst);
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compare_values('he, data);
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end
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initial begin
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clk <= 0;
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rst <= 1;
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up <= 0;
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ce <= 1;
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#50ns rst <= 0;
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end
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always begin
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#5ns clk <= ~clk;
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end
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final begin
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$display("Ending simulation at time %0t", $time);
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end
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endmodule : simple_tb
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