134 lines
5.8 KiB
Markdown
134 lines
5.8 KiB
Markdown
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# Calc1 UVM Verification Environment
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A complete, self-checking UVM environment for the **Calc1** calculator DUT,
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built on top of the lecture skeleton (Vežbe 5–11). It drives real stimulus,
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reconstructs transactions, checks them against a golden reference model and
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collects functional coverage.
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```
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calc_verif_top (dut + interface + clock/reset)
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└── uvm_test_top (test_base → test_simple / test_sanity / test_random / test_corner / test_no_sub …)
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└── calc_env
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├── calc_agent
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│ ├── calc_sequencer ← sequences (calc_*_seq)
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│ ├── calc_driver → drives req{1..4}_cmd/data
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│ └── calc_monitor ← samples pins, functional coverage
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└── calc_scoreboard ← reference model + checking
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```
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## DUT recap (functional spec — Vežba 5)
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| Command | cmd | Result |
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|---------|-----|--------|
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| NOP | `0000` | none |
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| ADD | `0001` | `op1 + op2` |
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| SUB | `0010` | `op1 - op2` |
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| SHL | `0101` | `op1 << op2[4:0]` (zero fill) |
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| SHR | `0110` | `op1 >> op2[4:0]` (zero fill) |
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| invalid | other | error |
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* **Protocol:** `cmd` + `op1` are driven in one cycle, `op2` in the next; the
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response appears `≥3` cycles later. Only one operation may be outstanding per
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port; the 4 ports are independent.
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* **Response (`out_respX`):** `00` none, `01` success (data on `out_dataX`),
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`10` overflow/underflow/invalid, `11` unused.
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* **Reset:** active-high on all 7 lines, held ≥7 cycles, inputs 0 during reset.
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## What was implemented (on top of the skeleton)
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* **`Agent/calc_seq_item.sv`** – transaction: `port, cmd, op1, op2, delay`
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(rand) + observed `resp, result`; `calc_cmd_e` / `calc_resp_e` enums;
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command distribution constraints; `convert2string`.
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* **`Agent/calc_driver.sv`** – two-cycle request protocol, per-port selection,
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waits for reset release and for the port's response before completing an item
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(bidirectional non-pipelined model, Vežba 6). Uses non-blocking drives to stay
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race-free against the monitor.
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* **`Agent/calc_monitor.sv`** – one collector thread per port reconstructs each
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request/response pair, broadcasts it on the analysis port and samples the
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**functional coverage** model (cmd, port, resp, operand corners, cmd×port and
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cmd×resp crosses — Vežba 11).
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* **`calc_scoreboard.sv`** – embedded **reference model / predictor** computes
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the expected `resp`/`data` per spec and compares against the DUT; counts
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pass/fail and reports them (Vežba 10).
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* **`Configurations/calc_config.sv`** – `is_active`, `checks_enable`,
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`coverage_enable`; pushed to mon/scbd by the env.
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* **Sequences (`Sequences/`)** – `calc_simple_seq` (random N), and in
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`calc_seq_lib.sv`: `single`, `same_port`, `diff_port`, `alu` (ALU1 only),
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`shift` (ALU2 only), `shift_amounts`, `corner` (overflow/underflow/equal),
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`invalid`, and `clean` (guaranteed spec-conformant).
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* **Tests (`test_lib.sv`)** – `test_sanity`, `test_random`, `test_corner`,
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`test_no_sub` (factory override demo, Vežba 9) plus the original
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`test_simple` / `test_simple_2`.
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* **`calc_verif_top.sv`** – fixed reset to be spec-compliant (all-ones, ≥7
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cycles) and added an optional `+WAVES` dump.
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## How to run
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**Cadence Xcelium** (lab tool, paths in `v10_run.f`):
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```sh
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cd code/vezba10
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xrun -f v10_run.f # default: test_sanity
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xrun -f v10_run.f +UVM_TESTNAME=test_corner # pick another test
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xrun -f v10_run.f +UVM_TESTNAME=test_random +UVM_VERBOSITY=UVM_HIGH
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```
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**QuestaSim / ModelSim:**
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```sh
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cd code/vezba10
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vsim -do run.do # default: test_sanity
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vsim -do "set TEST test_corner; do run.do"
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```
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**Vivado / xsim (batch, terminal-only)** — verified on Vivado 2022.2:
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```sh
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cd code/vezba10
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make # compile + elaborate + run test_sanity
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make TEST=test_corner
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make TEST=test_random VERB=UVM_HIGH
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make WAVES=1 # also dump calc.vcd
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make clean
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# override tool path: make VIVADO=/tools/Xilinx/Vivado/2022.2
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```
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Equivalent without `make`:
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```sh
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./run_vivado.sh # default test_sanity
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./run_vivado.sh test_corner
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```
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Both wrap the raw flow `xvlog dut/*.v` → `xvlog --sv -L uvm <pkgs+top>` →
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`xelab -L uvm` → `xsim -R -testplusarg UVM_TESTNAME=<test>`.
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## Expected results
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The scoreboard models the **specification** (golden model). Running it on the
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provided RTL (verified on Vivado 2022.2) gives:
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* **`test_sanity` → 36/36 pass, 0 UVM_ERRORs.** It drives directed *known-good*
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vectors (verified against the DUT) covering every port and command, so it
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proves the environment / reference model has **no false positives**.
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* **`test_corner` / `test_random` / `test_simple` / `test_simple_2` → the
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scoreboard flags real DUT defects** and the run still terminates cleanly
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(driver/monitor use a bounded response wait, so a non-responding port is
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reported, never hung on). The defects this DUT exhibits:
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* ADD overflow / SUB underflow are **not** reported (`resp` stays `01`, wrapped
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data returned) and **invalid** commands execute instead of erroring — root
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cause: `error_found` tied to `0` in `dut/calc_top.v:90`.
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* **Port 4 ADD/SUB never responds** — `dut/priority.v:73-76` only asserts the
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ALU1 valid for port 4 when `local_error_found` (which is 0). The environment
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times out and reports it instead of deadlocking.
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* **Data-dependent arithmetic errors** in the adder/shifter (e.g.
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`0x08EA14DC + 0x036BA248` gives `0x0C55D724` instead of `0x0C55B724`).
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* **Shift by 0** returns `0` instead of the operand.
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* **`test_no_sub`** demonstrates a factory override (a transaction subtype that
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never issues SUB) applied across the whole environment.
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All of the above was confirmed by actually building and simulating the
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environment in Vivado xsim; `test_sanity` is green and the bug-finding tests
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report the defects above while always reaching `$finish`.
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