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2026-06-12 07:53:32 +02:00
# ============================================================================
# QuestaSim / ModelSim run script for the Calc1 UVM environment.
# usage: vsim -do run.do
# pick a test: vsim -do "set TEST test_corner; do run.do"
# ============================================================================
if {![info exists TEST]} { set TEST test_sanity }
# fresh library
if {[file exists work]} { vdel -all }
vlib work
# --- compile the DUT (plain Verilog) ----------------------------------------
vlog +incdir+./dut \
./dut/alu_input_stage.v \
./dut/alu_output_stage.v \
./dut/exdbin_mac.v \
./dut/holdreg.v \
./dut/mux_out.v \
./dut/shifter.v \
./dut/priority.v \
./dut/calc_top.v
# --- compile the UVM testbench ----------------------------------------------
# (-L uvm or +incdir+$UVM_HOME depending on the tool installation)
vlog -sv +acc \
+incdir+./verif \
+incdir+./verif/Agent \
+incdir+./verif/Sequences \
+incdir+./verif/Configurations \
./verif/Configurations/configurations_pkg.sv \
./verif/Agent/calc_agent_pkg.sv \
./verif/Sequences/calc_seq_pkg.sv \
./verif/calc_test_pkg.sv \
./verif/calc_if.sv \
./verif/calc_verif_top.sv
# --- elaborate + run --------------------------------------------------------
vsim -coverage calc_verif_top +UVM_TESTNAME=$TEST +UVM_VERBOSITY=UVM_LOW -sv_seed random
run -all
# functional coverage report (optional)
coverage report -detail -cvg
quit -f