116 lines
4.2 KiB
Systemverilog
116 lines
4.2 KiB
Systemverilog
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`ifndef CALC_DRIVER_SV
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`define CALC_DRIVER_SV
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//-----------------------------------------------------------------------------
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// Calc1 driver.
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//
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// Protocol (Vezba 5):
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// * command + operand1 are driven in the same cycle,
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// * operand2 is driven in the next cycle (command line back to 0),
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// * a response appears on out_respX a few (>=3) cycles later.
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//
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// Only one request may be outstanding per port, so after issuing a request the
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// driver waits for that port's response before completing the item. This keeps
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// the very simple "bidirectional, non-pipelined" use model from Vezba 6.
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//-----------------------------------------------------------------------------
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class calc_driver extends uvm_driver#(calc_seq_item);
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`uvm_component_utils(calc_driver)
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virtual interface calc_if vif;
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function new(string name = "calc_driver", uvm_component parent = null);
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super.new(name,parent);
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endfunction
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
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endfunction : connect_phase
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task main_phase(uvm_phase phase);
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// start from a known idle state and wait until reset is released
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reset_inputs();
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wait_reset_done();
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forever begin
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seq_item_port.get_next_item(req);
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`uvm_info(get_type_name(),
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$sformatf("Driving: %s", req.convert2string()), UVM_HIGH)
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drive_item(req);
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seq_item_port.item_done();
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end
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endtask : main_phase
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// Drive a single transaction following the two-cycle request protocol and
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// wait for the corresponding response on the same port.
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task drive_item(calc_seq_item it);
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int unsigned wait_cnt;
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// optional idle gap before the request
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repeat (it.delay) @(posedge vif.clk);
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// cycle 1: command + operand1
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drive_req(it.port, it.cmd, it.op1);
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@(posedge vif.clk);
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// cycle 2: operand2, command de-asserted
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drive_req(it.port, CMD_NOP, it.op2);
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@(posedge vif.clk);
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// idle the port again while the pipeline produces the result
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drive_req(it.port, CMD_NOP, '0);
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// wait for this port's response (resp != 0), bounded so a non-responding
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// DUT cannot deadlock the test
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wait_cnt = 0;
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do begin
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@(posedge vif.clk);
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wait_cnt++;
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end while (get_resp(it.port) === RESP_NONE && wait_cnt < RSP_TIMEOUT);
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if (get_resp(it.port) === RESP_NONE)
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`uvm_warning(get_type_name(),
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$sformatf("No response on port %0d within %0d cycles (cmd=%s) - the scoreboard will flag this",
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it.port+1, RSP_TIMEOUT, it.cmd2string()))
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endtask : drive_item
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// Drive command/data onto the selected port, leaving the others untouched.
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task drive_req(bit [1:0] port, bit [CMD_WIDTH-1:0] cmd, bit [DATA_WIDTH-1:0] data);
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case (port)
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2'd0 : begin vif.req1_cmd_in <= cmd; vif.req1_data_in <= data; end
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2'd1 : begin vif.req2_cmd_in <= cmd; vif.req2_data_in <= data; end
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2'd2 : begin vif.req3_cmd_in <= cmd; vif.req3_data_in <= data; end
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2'd3 : begin vif.req4_cmd_in <= cmd; vif.req4_data_in <= data; end
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endcase
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endtask : drive_req
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// Combinational read of a port's response line.
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function bit [RESP_WIDTH-1:0] get_resp(bit [1:0] port);
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case (port)
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2'd0 : return vif.out_resp1;
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2'd1 : return vif.out_resp2;
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2'd2 : return vif.out_resp3;
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2'd3 : return vif.out_resp4;
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endcase
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endfunction
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// Drive all request lines to their idle (zero) state.
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task reset_inputs();
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vif.req1_cmd_in <= '0; vif.req1_data_in <= '0;
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vif.req2_cmd_in <= '0; vif.req2_data_in <= '0;
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vif.req3_cmd_in <= '0; vif.req3_data_in <= '0;
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vif.req4_cmd_in <= '0; vif.req4_data_in <= '0;
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endtask : reset_inputs
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task wait_reset_done();
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// reset is active-high (all ones); wait until it is fully released
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while (vif.rst !== '0) @(posedge vif.clk);
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`uvm_info(get_type_name(), "Reset released - starting to drive", UVM_LOW)
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endtask : wait_reset_done
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endclass : calc_driver
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`endif
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