207 lines
6.9 KiB
Systemverilog
207 lines
6.9 KiB
Systemverilog
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`ifndef CALC_MONITOR_SV
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`define CALC_MONITOR_SV
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//-----------------------------------------------------------------------------
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// Calc1 monitor.
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//
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// Passive component. One collector thread per port reconstructs a transaction
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// from the pin activity:
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// * a request starts when reqX_cmd_in != 0 -> capture cmd and operand1,
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// * operand2 is the data line on the following cycle,
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// * the matching response is the first cycle in which out_respX != 0.
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//
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// The completed transaction (stimulus + observed response/result) is broadcast
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// over the analysis port to the scoreboard, and functional coverage is sampled.
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//-----------------------------------------------------------------------------
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class calc_monitor extends uvm_monitor;
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// control fields
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bit checks_enable = 1;
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bit coverage_enable = 1;
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uvm_analysis_port #(calc_seq_item) item_collected_port;
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`uvm_component_utils_begin(calc_monitor)
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`uvm_field_int(checks_enable, UVM_DEFAULT)
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`uvm_field_int(coverage_enable, UVM_DEFAULT)
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`uvm_component_utils_end
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// The virtual interface used to view HDL signals.
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virtual interface calc_if vif;
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// number of transactions collected (per port and total)
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int unsigned num_collected;
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//--------------------------------------------------------------------------
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// Functional coverage model (Vezba 11).
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//--------------------------------------------------------------------------
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bit [CMD_WIDTH-1:0] cov_cmd;
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bit [1:0] cov_port;
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bit [RESP_WIDTH-1:0] cov_resp;
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bit [DATA_WIDTH-1:0] cov_op1;
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bit [DATA_WIDTH-1:0] cov_op2;
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covergroup calc_cg;
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option.per_instance = 1;
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option.name = "calc_functional_coverage";
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cp_cmd : coverpoint cov_cmd {
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bins add = {CMD_ADD};
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bins sub = {CMD_SUB};
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bins shl = {CMD_SHL};
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bins shr = {CMD_SHR};
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bins invalid = {[4'h3:4'h4], 4'h7, [4'h8:4'hF]};
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}
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cp_port : coverpoint cov_port {
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bins port1 = {2'd0};
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bins port2 = {2'd1};
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bins port3 = {2'd2};
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bins port4 = {2'd3};
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}
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// the monitor only emits an item once a real response is seen, so only
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// SUCCESS and ERROR are ever sampled here
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cp_resp : coverpoint cov_resp {
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bins success = {RESP_SUCCESS};
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bins error = {RESP_ERROR};
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}
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// interesting operand corners
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cp_op1 : coverpoint cov_op1 {
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bins zero = {32'h0000_0000};
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bins one = {32'h0000_0001};
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bins max = {32'hFFFF_FFFF};
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bins msb = {32'h8000_0000};
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bins others = default;
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}
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cp_op2 : coverpoint cov_op2 {
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bins zero = {32'h0000_0000};
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bins one = {32'h0000_0001};
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bins max = {32'hFFFF_FFFF};
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bins shamt = {[32'h2:32'h1F]}; // small shift amounts
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bins others = default;
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}
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// every legal command must be exercised on every port
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cx_cmd_port : cross cp_cmd, cp_port;
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// every command must be seen producing both success and error responses
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cx_cmd_resp : cross cp_cmd, cp_resp;
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endgroup
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function new(string name = "calc_monitor", uvm_component parent = null);
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super.new(name,parent);
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item_collected_port = new("item_collected_port", this);
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calc_cg = new();
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endfunction
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
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endfunction : connect_phase
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task main_phase(uvm_phase phase);
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wait_reset_done();
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// launch one independent collector per port
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for (int p = 0; p < NUM_PORTS; p++) begin
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automatic int port = p;
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fork
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collect_port(port[1:0]);
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join_none
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end
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endtask : main_phase
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// Collect every request/response pair seen on a single port.
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task collect_port(bit [1:0] port);
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calc_seq_item it;
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int unsigned wait_cnt;
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forever begin
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// wait for the start of a request on this port
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do @(posedge vif.clk); while (get_cmd(port) === CMD_NOP || vif.rst !== '0);
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it = calc_seq_item::type_id::create($sformatf("it_p%0d", port));
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it.port = port;
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it.cmd = get_cmd(port);
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it.op1 = get_data(port);
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// operand2 is presented on the next cycle
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@(posedge vif.clk);
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it.op2 = get_data(port);
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// wait for the response on this port (bounded - a non-responding DUT
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// is reported, not waited on forever); resp stays NONE on timeout so
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// the scoreboard flags the missing response
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wait_cnt = 0;
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do begin
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@(posedge vif.clk);
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wait_cnt++;
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end while (get_resp(port) === RESP_NONE && wait_cnt < RSP_TIMEOUT);
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it.resp = get_resp(port);
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it.result = get_out_data(port);
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num_collected++;
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`uvm_info(get_type_name(),
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$sformatf("Collected: %s", it.convert2string()), UVM_MEDIUM)
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if (coverage_enable) sample_coverage(it);
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item_collected_port.write(it);
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end
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endtask : collect_port
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function void sample_coverage(calc_seq_item it);
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cov_cmd = it.cmd;
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cov_port = it.port;
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cov_resp = it.resp;
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cov_op1 = it.op1;
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cov_op2 = it.op2;
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calc_cg.sample();
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endfunction
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//--- per-port signal accessors -------------------------------------------
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function bit [CMD_WIDTH-1:0] get_cmd(bit [1:0] port);
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case (port)
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2'd0 : return vif.req1_cmd_in;
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2'd1 : return vif.req2_cmd_in;
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2'd2 : return vif.req3_cmd_in;
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2'd3 : return vif.req4_cmd_in;
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endcase
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endfunction
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function bit [DATA_WIDTH-1:0] get_data(bit [1:0] port);
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case (port)
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2'd0 : return vif.req1_data_in;
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2'd1 : return vif.req2_data_in;
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2'd2 : return vif.req3_data_in;
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2'd3 : return vif.req4_data_in;
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endcase
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endfunction
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function bit [RESP_WIDTH-1:0] get_resp(bit [1:0] port);
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case (port)
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2'd0 : return vif.out_resp1;
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2'd1 : return vif.out_resp2;
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2'd2 : return vif.out_resp3;
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2'd3 : return vif.out_resp4;
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endcase
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endfunction
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function bit [DATA_WIDTH-1:0] get_out_data(bit [1:0] port);
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case (port)
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2'd0 : return vif.out_data1;
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2'd1 : return vif.out_data2;
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2'd2 : return vif.out_data3;
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2'd3 : return vif.out_data4;
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endcase
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endfunction
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task wait_reset_done();
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while (vif.rst !== '0) @(posedge vif.clk);
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endtask : wait_reset_done
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function void report_phase(uvm_phase phase);
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`uvm_info(get_type_name(),
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$sformatf("Monitor collected %0d transactions, functional coverage = %0.2f%%",
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num_collected, calc_cg.get_coverage()), UVM_LOW)
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endfunction : report_phase
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endclass : calc_monitor
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`endif
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