28 lines
872 B
Systemverilog
28 lines
872 B
Systemverilog
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`ifndef CALC_SIMPLE_SEQ_SV
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`define CALC_SIMPLE_SEQ_SV
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//-----------------------------------------------------------------------------
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// Default random sequence: send a configurable number of fully random,
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// legal+illegal transactions to random ports.
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//-----------------------------------------------------------------------------
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class calc_simple_seq extends calc_base_seq;
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`uvm_object_utils (calc_simple_seq)
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rand int unsigned num_of_tr = 10; // default when the sequence is not randomized
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constraint c_num { num_of_tr inside {[1:20]}; }
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function new(string name = "calc_simple_seq");
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super.new(name);
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endfunction
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virtual task body();
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`uvm_info(get_type_name(), $sformatf("Generating %0d random transactions", num_of_tr), UVM_LOW)
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repeat (num_of_tr)
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`uvm_do(req)
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endtask : body
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endclass : calc_simple_seq
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`endif
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