42 lines
990 B
Systemverilog
42 lines
990 B
Systemverilog
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`ifndef MEMORY_SV
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`define MEMORY_SV
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module memory #(
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parameter ADDR_WIDTH = 2,
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parameter DATA_WIDTH = 8
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)
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(
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input logic clk,
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input logic rst,
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input logic [ADDR_WIDTH-1 : 0] addr_i,
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input logic rw_i,
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input logic en_i,
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input logic [DATA_WIDTH-1 : 0] data_i,
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output logic [DATA_WIDTH-1 : 0] data_o
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);
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logic [DATA_WIDTH-1 : 0] mem [2**ADDR_WIDTH];
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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for(int i = 0; i < 2**ADDR_WIDTH; i++) begin
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mem[i] = 0;
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end
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end
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else begin
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if(en_i) begin
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if(rw_i) begin
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mem[addr_i] <= data_i;
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end
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else begin
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data_o <= mem[addr_i];
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end
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end
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end
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end
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endmodule : memory
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`endif
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