41 lines
808 B
Systemverilog
41 lines
808 B
Systemverilog
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class transaction;
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rand bit [1 : 0] addr;
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rand bit [7 : 0] data;
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function void display_transaction();
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$display("\taddr = %0h", this.addr);
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$display("\tdata = %0h", this.data);
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endfunction : display_transaction
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endclass : transaction
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module top;
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transaction tr;
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initial begin
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tr = new;
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$display("Initial");
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tr.display_transaction();
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assert(tr.randomize());
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$display("Randomize all");
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tr.display_transaction();
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assert(tr.randomize(data));
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$display("Randomize just data");
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tr.display_transaction();
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end
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// Rezultat izvrsavanja:
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//
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// Initial
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// addr = 0
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// data = 0
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// Randomize all
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// addr = 2
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// data = 1d
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// Randomize just data
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// addr = 2
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// data = 9a
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endmodule : top
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