31 lines
892 B
Systemverilog
31 lines
892 B
Systemverilog
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`ifndef CALC_BASE_SEQ_SV
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`define CALC_BASE_SEQ_SV
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class calc_base_seq extends uvm_sequence#(calc_seq_item);
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`uvm_object_utils(calc_base_seq)
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`uvm_declare_p_sequencer(calc_sequencer)
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function new(string name = "calc_base_seq");
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super.new(name);
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endfunction
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// objections are raised in pre_body
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virtual task pre_body();
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uvm_phase phase = get_starting_phase();
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if (phase != null)
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phase.raise_objection(this, {"Running sequence '", get_full_name(), "'"});
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uvm_test_done.set_drain_time(this, 200ms);
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endtask : pre_body
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// objections are dropped in post_body
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virtual task post_body();
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uvm_phase phase = get_starting_phase();
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if (phase != null)
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phase.drop_objection(this, {"Completed sequence '", get_full_name(), "'"});
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endtask : post_body
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endclass : calc_base_seq
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`endif
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