45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
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class calc_monitor extends uvm_monitor;
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// control fileds
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bit checks_enable = 1;
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bit coverage_enable = 1;
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uvm_analysis_port #(calc_seq_item) item_collected_port;
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`uvm_component_utils_begin(calc_monitor)
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`uvm_field_int(checks_enable, UVM_DEFAULT)
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`uvm_field_int(coverage_enable, UVM_DEFAULT)
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`uvm_component_utils_end
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// The virtual interface used to drive and view HDL signals.
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virtual interface calc_if vif;
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// current transaction
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calc_seq_item curr_it;
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// coverage can go here
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// ...
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function new(string name = "calc_monitor", uvm_component parent = null);
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super.new(name,parent);
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if (!uvm_config_db#(virtual calc_if)::get(null, "*", "calc_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
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endfunction
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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endfunction : connect_phase
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task main_phase(uvm_phase phase);
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// forever begin
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// curr_it = calc_seq_item::type_id::create("curr_it", this);
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// ...
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// collect transactions
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// ...
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// item_collected_port.write(curr_it);
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// end
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endtask : main_phase
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endclass : calc_monitor
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