30 lines
819 B
Systemverilog
30 lines
819 B
Systemverilog
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`ifndef TEST_BASE_SV
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`define TEST_BASE_SV
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class test_base extends uvm_test;
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`uvm_component_utils(test_base)
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calc_driver drv;
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calc_monitor mon;
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calc_sequencer seqr;
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calc_seq_item seq_item1;
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function new(string name = "test_base", uvm_component parent = null);
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super.new(name,parent);
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endfunction : new
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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drv = calc_driver::type_id::create("drv", this);
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mon = calc_monitor::type_id::create("mon", this);
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seqr = calc_sequencer::type_id::create("seqr", this);
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endfunction : build_phase
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function void connect_phase(uvm_phase phase);
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drv.seq_item_port.connect(seqr.seq_item_export);
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endfunction : connect_phase
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endclass : test_base
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`endif
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