29 lines
685 B
Systemverilog
29 lines
685 B
Systemverilog
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`ifndef TEST_SIMPLE_SV
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`define TEST_SIMPLE_SV
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class test_simple extends test_base;
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`uvm_component_utils(test_simple)
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calc_simple_seq simple_seq;
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function new(string name = "test_simple", uvm_component parent = null);
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super.new(name,parent);
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endfunction : new
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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simple_seq = calc_simple_seq::type_id::create("simple_seq");
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endfunction : build_phase
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task main_phase(uvm_phase phase);
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phase.raise_objection(this);
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simple_seq.start(seqr);
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#100ms;
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phase.drop_objection(this);
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endtask : main_phase
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endclass
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`endif
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