101 lines
2.3 KiB
Systemverilog
101 lines
2.3 KiB
Systemverilog
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import uvm_pkg::*; // import the UVM library
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`include "uvm_macros.svh" // Include the UVM macros
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// example transaction
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class Transaction extends uvm_sequence_item;
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bit [1 : 0] addr;
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bit [7 : 0] data;
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`uvm_object_utils_begin(Transaction)
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`uvm_field_int(addr, UVM_DEFAULT)
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`uvm_field_int(data, UVM_DEFAULT)
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`uvm_object_utils_end
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constraint addr_data_constraint {
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addr == 5;
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5 < data < 10;
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}
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function new (string name = "Transaction");
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super.new(name);
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endfunction : new
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endclass : Transaction
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// test
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class test extends uvm_test;
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`uvm_component_utils(test)
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bit [2 : 0] i;
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Transaction tr_queue[$];
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bit e1, e2;
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function new(string name = "test", uvm_component parent = null);
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super.new(name, parent);
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endfunction : new
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// build phase - fill tr_queue with 10 random transactions
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function void build_phase(uvm_phase phase);
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Transaction tr;
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super.build_phase(phase);
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`uvm_info(get_type_name(), "Starting build phase ...", UVM_HIGH)
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tr = Transaction::type_id::create("tr");
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for(i = 0; i < 10; i++) begin
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tr.randomize();
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tr_queue.push_back(tr);
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end
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endfunction : build_phase
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task run_phase(uvm_phase phase);
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`uvm_info(get_type_name(), "Starting run phase ...", UVM_HIGH)
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phase.raise_objection(this);
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fork
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generate_random_events();
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display_tr();
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join_any;
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disable fork;
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phase.drop_objection(this);
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endtask : run_phase
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task generate_random_events();
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forever begin
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#($urandom_range(10,1)); // delay
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if($urandom_range(1)) begin
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`uvm_info(get_type_name(), "e1 changed...", UVM_HIGH)
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e1 = !e1;
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end
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else begin
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`uvm_info(get_type_name(), "e2 changed...", UVM_HIGH)
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e2 = !e2;
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end
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end
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endtask : generate_random_events
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task display_tr();
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Transaction tr;
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while(tr_queue.size()) begin
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@(e1 || e2);
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tr = tr_queue[i];
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`uvm_info(get_type_name(),
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$sformatf("Transaction: \n%s", tr.sprint()),
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UVM_HIGH)
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end
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endtask : display_tr
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endclass : test
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// top module
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module top();
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initial begin
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run_test("test");
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end
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endmodule : top
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