64 lines
2.0 KiB
Systemverilog
64 lines
2.0 KiB
Systemverilog
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module calc_verif_top;
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import uvm_pkg::*; // import the UVM library
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`include "uvm_macros.svh" // Include the UVM macros
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import calc_test_pkg::*;
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logic clk;
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logic [6 : 0] rst;
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// interface
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calc_if calc_vif(clk, rst);
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// DUT
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calc_top DUT(
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.c_clk ( clk ),
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.reset ( rst ),
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.out_data1 ( calc_vif.out_data1 ),
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.out_data2 ( calc_vif.out_data2 ),
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.out_data3 ( calc_vif.out_data3 ),
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.out_data4 ( calc_vif.out_data4 ),
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.out_resp1 ( calc_vif.out_resp1 ),
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.out_resp2 ( calc_vif.out_resp2 ),
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.out_resp3 ( calc_vif.out_resp3 ),
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.out_resp4 ( calc_vif.out_resp4 ),
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.req1_cmd_in ( calc_vif.req1_cmd_in ),
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.req1_data_in ( calc_vif.req1_data_in ),
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.req2_cmd_in ( calc_vif.req2_cmd_in ),
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.req2_data_in ( calc_vif.req2_data_in ),
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.req3_cmd_in ( calc_vif.req3_cmd_in ),
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.req3_data_in ( calc_vif.req3_data_in ),
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.req4_cmd_in ( calc_vif.req4_cmd_in ),
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.req4_data_in ( calc_vif.req4_data_in )
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);
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// run test
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initial begin
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uvm_config_db#(virtual calc_if)::set(null, "uvm_test_top.env", "calc_if", calc_vif);
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run_test();
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end
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// optional waveform dump : add +WAVES on the command line
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initial begin
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if ($test$plusargs("WAVES")) begin
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$dumpfile("calc.vcd");
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$dumpvars(0, calc_verif_top);
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end
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end
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// clock and reset init.
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// Reset is active-high on all 7 lines and must be held for at least
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// 7 clock cycles to propagate through the design (Vezba 5).
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initial begin
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clk = 0;
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rst = '1;
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repeat (8) @(posedge clk);
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rst = '0;
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end
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// clock generation
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always #50 clk = ~clk;
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endmodule : calc_verif_top
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