50 lines
1.4 KiB
Systemverilog
50 lines
1.4 KiB
Systemverilog
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`ifndef TEST_SIMPLE_SV
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`define TEST_SIMPLE_SV
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class test_simple extends uvm_test;
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`uvm_component_utils(test_simple)
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virtual interface calc_if vif;
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function new(string name = "test_simple", uvm_component parent = null);
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super.new(name,parent);
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endfunction : new
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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`uvm_info(get_type_name(), "Starting build phase...", UVM_LOW)
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// Preuzimanje virtuelnog interfejsa iz konfiguracione baze podataka.
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if (!uvm_config_db#(virtual calc_if)::get(null, "*", "calc_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
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// ...
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endfunction : build_phase
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task main_phase(uvm_phase phase);
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super.main_phase(phase);
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phase.raise_objection(this); //objasnjenje u materijalu za vezbu 6
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`uvm_info(get_type_name(), "Starting main phase...", UVM_LOW)
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//postavljanje komande
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vif.req1_cmd_in = 4'b0001;
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//postavljanje prvog podatka
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vif.req1_data_in = 32'h0001;
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//Cekanje 1 takt
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@(posedge vif.clk);
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//Uklanjanje komande
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vif.req1_cmd_in = 4'b0000;
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//Postavljanje drugog podatka
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vif.req1_data_in = 32'h0002;
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// ...
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#1000ns;
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phase.drop_objection(this); //objasnjenje u materijalu za vezbu 6
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endtask : main_phase
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endclass : test_simple
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`endif
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