48 lines
1.8 KiB
Systemverilog
48 lines
1.8 KiB
Systemverilog
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class calc_agent extends uvm_agent;
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// components
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calc_driver drv;
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calc_sequencer seqr;
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calc_monitor mon;
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virtual interface calc_if vif;
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// configuration
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calc_config cfg;
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int value;
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`uvm_component_utils_begin (calc_agent)
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`uvm_field_object(cfg, UVM_DEFAULT)
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`uvm_component_utils_end
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function new(string name = "calc_agent", uvm_component parent = null);
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super.new(name,parent);
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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/************Geting from configuration database*******************/
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if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
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if(!uvm_config_db#(calc_config)::get(this, "", "calc_config", cfg))
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`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
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/*****************************************************************/
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/************Setting to configuration database********************/
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uvm_config_db#(virtual calc_if)::set(this, "*", "calc_if", vif);
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/*****************************************************************/
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mon = calc_monitor::type_id::create("mon", this);
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if(cfg.is_active == UVM_ACTIVE) begin
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drv = calc_driver::type_id::create("drv", this);
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seqr = calc_sequencer::type_id::create("seqr", this);
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end
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endfunction : build_phase
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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if(cfg.is_active == UVM_ACTIVE) begin
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drv.seq_item_port.connect(seqr.seq_item_export);
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end
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endfunction : connect_phase
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endclass : calc_agent
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