117 lines
4.6 KiB
Systemverilog
117 lines
4.6 KiB
Systemverilog
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`ifndef CALC_SCOREBOARD_SV
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`define CALC_SCOREBOARD_SV
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//-----------------------------------------------------------------------------
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// Calc1 scoreboard (self-checking, reference-model based - Vezba 10).
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//
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// For every transaction collected by the monitor, the embedded reference model
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// (predictor) computes the expected response/result from the stimulus and
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// compares it against what the DUT actually produced. Mismatches are reported
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// as UVM_ERROR.
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//-----------------------------------------------------------------------------
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class calc_scoreboard extends uvm_scoreboard;
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// control fields
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bit checks_enable = 1;
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bit coverage_enable = 1;
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// TLM port connecting the scoreboard to the monitor
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uvm_analysis_imp#(calc_seq_item, calc_scoreboard) item_collected_imp;
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// bookkeeping
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int unsigned num_of_tr;
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int unsigned num_passed;
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int unsigned num_failed;
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`uvm_component_utils_begin(calc_scoreboard)
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`uvm_field_int(checks_enable, UVM_DEFAULT)
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`uvm_field_int(coverage_enable, UVM_DEFAULT)
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`uvm_component_utils_end
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function new(string name = "calc_scoreboard", uvm_component parent = null);
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super.new(name,parent);
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item_collected_imp = new("item_collected_imp", this);
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endfunction : new
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//--------------------------------------------------------------------------
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// Reference model / predictor.
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// Computes the expected response and result for a Calc1 command, following
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// the functional specification (Vezba 5, Tabela 6/7/8).
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// All arithmetic is unsigned.
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//--------------------------------------------------------------------------
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function void predict(input bit [CMD_WIDTH-1:0] cmd,
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input bit [DATA_WIDTH-1:0] op1,
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input bit [DATA_WIDTH-1:0] op2,
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output bit [RESP_WIDTH-1:0] exp_resp,
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output bit [DATA_WIDTH-1:0] exp_data);
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bit [DATA_WIDTH:0] tmp; // one extra bit to catch carry/borrow
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exp_data = '0;
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case (cmd)
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CMD_ADD : begin
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tmp = {1'b0, op1} + {1'b0, op2};
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if (tmp[DATA_WIDTH]) exp_resp = RESP_ERROR; // overflow
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else begin exp_resp = RESP_SUCCESS; exp_data = tmp[DATA_WIDTH-1:0]; end
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end
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CMD_SUB : begin
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if (op1 < op2) exp_resp = RESP_ERROR; // underflow
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else begin exp_resp = RESP_SUCCESS; exp_data = op1 - op2; end
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end
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CMD_SHL : begin
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exp_resp = RESP_SUCCESS;
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exp_data = op1 << op2[4:0];
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end
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CMD_SHR : begin
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exp_resp = RESP_SUCCESS;
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exp_data = op1 >> op2[4:0];
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end
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default : begin
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exp_resp = RESP_ERROR; // invalid command
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end
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endcase
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endfunction : predict
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//--------------------------------------------------------------------------
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// Analysis-port callback: invoked by the monitor for each collected item.
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//--------------------------------------------------------------------------
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function void write(calc_seq_item tr);
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bit [RESP_WIDTH-1:0] exp_resp;
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bit [DATA_WIDTH-1:0] exp_data;
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bit ok;
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num_of_tr++;
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if (!checks_enable) return;
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predict(tr.cmd, tr.op1, tr.op2, exp_resp, exp_data);
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// The result data is only meaningful for a successful operation.
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ok = (tr.resp === exp_resp) &&
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((exp_resp !== RESP_SUCCESS) || (tr.result === exp_data));
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if (ok) begin
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num_passed++;
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`uvm_info(get_type_name(),
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$sformatf("PASS: %s | expected resp=%0d data=0x%08h",
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tr.convert2string(), exp_resp, exp_data), UVM_HIGH)
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end
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else begin
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num_failed++;
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`uvm_error(get_type_name(),
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$sformatf("MISMATCH on port %0d, cmd=%s op1=0x%08h op2=0x%08h : expected resp=%0d data=0x%08h, got resp=%0d data=0x%08h",
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tr.port+1, tr.cmd2string(), tr.op1, tr.op2,
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exp_resp, exp_data, tr.resp, tr.result))
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end
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endfunction : write
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function void report_phase(uvm_phase phase);
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`uvm_info(get_type_name(),
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$sformatf("Scoreboard examined %0d transactions: %0d passed, %0d failed",
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num_of_tr, num_passed, num_failed), UVM_LOW)
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if (num_failed != 0)
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`uvm_warning(get_type_name(),
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$sformatf("%0d transaction(s) did NOT match the reference model", num_failed))
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endfunction : report_phase
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endclass : calc_scoreboard
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`endif
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