109 lines
3.0 KiB
Plaintext
109 lines
3.0 KiB
Plaintext
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o
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%s %s
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410* simulator2$
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Vivado Simulator2default:default2
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v2022.22default:defaultZ43-3977h px<04>
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q
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%s
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* simulator2T
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@Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.2default:defaulth px<04>
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<EFBFBD>
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Running: %s
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333* simulator2<72>
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v/tools/Xilinx/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --nolog -L uvm -timescale 1ns/10ps calc_verif_top -s calc_sim 2default:defaultZ43-3449h px<04>
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l
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.Multi-threading is on. Using %s slave threads
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406* simulator2
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102default:defaultZ43-3954h px<04>
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B
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Starting static elaboration
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342* simulatorZ43-3458h px<04>
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G
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!Pass Through NonSizing Optimizer
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685* simulatorZ43-4537h px<04>
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C
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Completed static elaboration
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280* simulatorZ43-3396h px<04>
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M
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'Starting simulation data flow analysis
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341* simulatorZ43-3457h px<04>
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<EFBFBD>
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lFile : %s, Line : %s, RANDC variable size more than 8 bits. This will be treated as a RAND variable instead.669* simulator2<72>
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p/proj/xbuilds/SWIP/9999.0_0921_2117/installs/lin64/Vivado/2023.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv2default:default2
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259942default:defaultZ43-4468h px<06>
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N
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(Completed simulation data flow analysis
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279* simulatorZ43-3395h px<04>
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d
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%Time Resolution for simulation is %s
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344* simulator2
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1ps2default:defaultZ43-3460h px<04>
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\
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Compiling %s
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389* simulator2'
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package uvm.uvm_pkg2default:defaultZ43-3505h px<04>
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X
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Compiling %s
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389* simulator2#
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package std.std2default:defaultZ43-3505h px<04>
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d
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Compiling %s
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389* simulator2/
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package work.calc_agent_pkg2default:defaultZ43-3505h px<04>
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h
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Compiling %s
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389* simulator23
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package work.configurations_pkg2default:defaultZ43-3505h px<04>
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c
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Compiling %s
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389* simulator2.
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package work.calc_test_pkg2default:defaultZ43-3505h px<04>
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b
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Compiling %s
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389* simulator2-
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package work.calc_seq_pkg2default:defaultZ43-3505h px<04>
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\
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Compiling module %s405* simulator2!
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work.calc_if
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2default:defaultZ43-3953h px<04>
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_
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Compiling module %s405* simulator2$
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work.exdbin_mac
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2default:defaultZ43-3953h px<04>
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\
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Compiling module %s405* simulator2!
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work.holdreg
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2default:defaultZ43-3953h px<04>
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d
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Compiling module %s405* simulator2)
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work.alu_input_stage
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2default:defaultZ43-3953h px<04>
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\
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Compiling module %s405* simulator2!
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work.mux_out
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2default:defaultZ43-3953h px<04>
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e
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Compiling module %s405* simulator2*
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work.alu_output_stage
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2default:defaultZ43-3953h px<04>
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^
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Compiling module %s405* simulator2#
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work.priority1
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2default:defaultZ43-3953h px<04>
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\
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Compiling module %s405* simulator2!
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work.shifter
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2default:defaultZ43-3953h px<04>
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]
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Compiling module %s405* simulator2"
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work.calc_top
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2default:defaultZ43-3953h px<04>
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c
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Compiling module %s405* simulator2(
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work.calc_verif_top
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2default:defaultZ43-3953h px<04>
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a
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Built simulation snapshot %s
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278* simulator2
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calc_sim2default:defaultZ43-3394h px<04>
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