43 lines
730 B
Systemverilog
43 lines
730 B
Systemverilog
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`ifndef TOP_SV
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`define TOP_SV
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`include "v2_memory.sv"
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`include "v2_memory_if.sv"
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`include "v2_memory_pkg.sv"
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module top;
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import memory_pkg::*;
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bit clk;
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bit rst;
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memory_if mem_if(clk, rst);
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memory DUT (
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.clk (clk),
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.rst (rst),
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.addr_i (mem_if.addr),
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.rw_i (mem_if.rw),
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.en_i (mem_if.en),
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.data_i (mem_if.data_i),
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.data_o (mem_if.data_o)
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);
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driver drv = new(mem_if);
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initial begin
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clk = 0;
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rst = 1;
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#5 rst =0;
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#500 $finish();
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end
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always #5 clk = ~clk;
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initial drv.run();
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endmodule : top
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`endif
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