24 lines
674 B
Systemverilog
24 lines
674 B
Systemverilog
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`ifndef TEST_SIMPLE_2_SV
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`define TEST_SIMPLE_2_SV
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class test_simple_2 extends test_base;
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`uvm_component_utils(test_simple_2)
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function new(string name = "test_simple_2", uvm_component parent = null);
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super.new(name,parent);
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endfunction : new
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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uvm_config_db#(uvm_object_wrapper)::set(this,
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"seqr.main_phase",
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"default_sequence",
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calc_simple_seq::type_id::get());
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endfunction : build_phase
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endclass
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`endif
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