added gitignore

.gitignore

@@ -0,0 +1,47 @@
+# ============================================================================
+# Simulation build artifacts — none of this belongs in the repo, it is all
+# regenerated by the run scripts (Makefile / run_vivado.sh / run.do / *.f).
+# ============================================================================
+
+# ---- Vivado / xsim ----
+xsim.dir/
+xsim.covdb/
+.Xil/
+*.wdb
+*.jou
+*.pb
+*.wcfg
+xvlog.log
+xelab.log
+xsim.log
+xsimcrash.log
+webtalk*
+usage_statistics_webtalk.*
+
+# ---- QuestaSim / ModelSim ----
+work/
+transcript
+vsim.wlf
+vsim_stacktrace.vstf
+modelsim.ini
+*.mti
+
+# ---- Cadence Xcelium / Incisive ----
+xcelium.d/
+INCA_libs/
+xrun.history
+xrun.log
+.simvision/
+*.shm/
+waves.shm/
+
+# ---- UVM / misc run output ----
+tr_db.log
+*.vcd
+
+# ---- Editor / OS junk ----
+.vscode/
+*~
+*.swp
+*.bak
+.DS_Store

code/vezba10/tr_db.log

@@ -1,7 +0,0 @@
-  CREATE_STREAM @0 {NAME:rnd T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:655}
-  CREATE_STREAM @43750000 {NAME:alu T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:1297}
-  CREATE_STREAM @59350000 {NAME:sh T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:1423}
-  CREATE_STREAM @65350000 {NAME:dp T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:1643}
-  CREATE_STREAM @82950000 {NAME:sp T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:1755}
-  CREATE_STREAM @87650000 {NAME:sa T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:1851}
-  CREATE_STREAM @94950000 {NAME:cor T:Transactions SCOPE:uvm_test_top.env.agent.seqr STREAM:2001}

code/vezba10/v9_run.f~

@@ -1,33 +0,0 @@
--uvmhome "/eda/cadence/2019-20/RHELx86/XCELIUM_19.03.013/tools/methodology/UVM/CDNS-1.2/" 
--uvm +UVM_TESTNAME=test_simple
--sv +incdir+./verif
--sv +incdir+./verif/Agent
--sv +incdir+./verif/Sequences
--sv +incdir+./verif/Configurations
- 
- ./dut/alu_input_stage.v
- ./dut/alu_output_stage.v
- ./dut/exdbin_mac.v
- ./dut/holdreg.v
- ./dut/mux_out.v
- ./dut/shifter.v
- ./dut/priority.v
- ./dut/calc_top.v
-
-
--sv ./verif/Configurations/configurations_pkg.sv
--sv ./verif/Agent/v9_calc_agent_pkg.sv
--sv ./verif/Sequences/v9_calc_seq_pkg.sv
--sv ./verif/v9_calc_test_pkg.sv
--sv ./verif/calc_if.sv
-
--sv ./verif/v9_calc_verif_top.sv
-
-
- 
-
-#-LINEDEBUG
--access +rwc
--disable_sem2009
--nowarn "MEMODR"
--timescale 1ns/10ps

code/vezba10/xsim.dir/calc_sim/Compile_Options.txt

@@ -1 +0,0 @@
---nolog -L "uvm" -timescale "1ns/10ps" "calc_verif_top" -s "calc_sim" 

code/vezba10/xsim.dir/calc_sim/xsimSettings.ini

@@ -1,50 +0,0 @@
-[General]
-ARRAY_DISPLAY_LIMIT=512
-RADIX=hex
-TIME_UNIT=ns
-TRACE_LIMIT=2147483647
-VHDL_ENTITY_SCOPE_FILTER=true
-VHDL_PACKAGE_SCOPE_FILTER=false
-VHDL_BLOCK_SCOPE_FILTER=true
-VHDL_PROCESS_SCOPE_FILTER=false
-VHDL_PROCEDURE_SCOPE_FILTER=false
-VERILOG_MODULE_SCOPE_FILTER=true
-VERILOG_PACKAGE_SCOPE_FILTER=false
-VERILOG_BLOCK_SCOPE_FILTER=false
-VERILOG_TASK_SCOPE_FILTER=false
-VERILOG_PROCESS_SCOPE_FILTER=false
-INPUT_OBJECT_FILTER=true
-OUTPUT_OBJECT_FILTER=true
-INOUT_OBJECT_FILTER=true
-INTERNAL_OBJECT_FILTER=true
-CONSTANT_OBJECT_FILTER=true
-VARIABLE_OBJECT_FILTER=true
-INPUT_PROTOINST_FILTER=true
-OUTPUT_PROTOINST_FILTER=true
-INOUT_PROTOINST_FILTER=true
-INTERNAL_PROTOINST_FILTER=true
-CONSTANT_PROTOINST_FILTER=true
-VARIABLE_PROTOINST_FILTER=true
-SCOPE_NAME_COLUMN_WIDTH=0
-SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
-SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
-OBJECT_NAME_COLUMN_WIDTH=0
-OBJECT_VALUE_COLUMN_WIDTH=0
-OBJECT_DATA_TYPE_COLUMN_WIDTH=0
-PROCESS_NAME_COLUMN_WIDTH=0
-PROCESS_TYPE_COLUMN_WIDTH=0
-FRAME_INDEX_COLUMN_WIDTH=0
-FRAME_NAME_COLUMN_WIDTH=0
-FRAME_FILE_NAME_COLUMN_WIDTH=0
-FRAME_LINE_NUM_COLUMN_WIDTH=0
-LOCAL_NAME_COLUMN_WIDTH=0
-LOCAL_VALUE_COLUMN_WIDTH=0
-LOCAL_DATA_TYPE_COLUMN_WIDTH=0
-PROTO_NAME_COLUMN_WIDTH=0
-PROTO_VALUE_COLUMN_WIDTH=0
-INPUT_LOCAL_FILTER=1
-OUTPUT_LOCAL_FILTER=1
-INOUT_LOCAL_FILTER=1
-INTERNAL_LOCAL_FILTER=1
-CONSTANT_LOCAL_FILTER=1
-VARIABLE_LOCAL_FILTER=1

code/vezba10/xsim.dir/calc_sim/xsim_script.tcl

@@ -1 +0,0 @@
-xsim {calc_sim} -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -autoloadwcfg -runall -sv_seed random

code/vezba10/xsim.dir/calc_sim/xsimkernel.log

@@ -1,7 +0,0 @@
-Running: xsim.dir/calc_sim/xsimk -runall -sv_seed random -simmode gui -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -wdb calc_sim.wdb -simrunnum 0 -socket 49855
-Design successfully loaded
-Design Loading Memory Usage: 44568 KB (Peak: 44568 KB)
-Design Loading CPU Usage: 20 ms
-Simulation completed
-Simulation Memory Usage: 139376 KB (Peak: 183836 KB)
-Simulation CPU Usage: 120 ms

code/vezba10/xsim.dir/work/work.rlx

@@ -1,34 +0,0 @@
-0.7
-2020.2
-Oct 14 2022
-05:07:14
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_input_stage.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_output_stage.v,,alu_input_stage,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_output_stage.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/calc_top.v,,alu_output_stage,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/calc_top.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/exdbin_mac.v,,calc_top,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/exdbin_mac.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/holdreg.v,,exdbin_mac,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/holdreg.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/mux_out.v,,holdreg,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/mux_out.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/priority.v,,mux_out,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/priority.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/shifter.v,,priority1,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/dut/shifter.v,1680513656,verilog,,,,shifter,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent.sv,1680513570,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv,1680513570,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_seq_item.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_sequencer.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_driver.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_monitor.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent.sv,calc_agent_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_driver.sv,1781194218,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_monitor.sv,1781194229,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_seq_item.sv,1781194204,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_sequencer.sv,1680513570,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/calc_config.sv,1781190521,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/configurations_pkg.sv,1680513570,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/calc_config.sv,configurations_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_base_seq.sv,1781190541,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_lib.sv,1781194763,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv,1781190610,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_base_seq.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_simple_seq.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_lib.sv,calc_seq_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_simple_seq.sv,1781190733,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_env.sv,1781190530,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,1680513570,systemVerilog,,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,,calc_if,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_scoreboard.sv,1781190500,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,1781190646,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_scoreboard.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_env.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_base.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple_2.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_lib.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,calc_test_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,1781190673,systemVerilog,,,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh,calc_verif_top,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_base.sv,1680513570,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_lib.sv,1781194773,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple.sv,1781190742,verilog,,,,,,,,,,,,
-/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple_2.sv,1781194936,verilog,,,,,,,,,,,,
-/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh,1665704903,verilog,,,,,,,,,,,,

code/vezba10/xsim.jou

@@ -1,14 +0,0 @@
-#-----------------------------------------------------------
-# xsim v2022.2 (64-bit)
-# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
-# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
-# Start of session at: Thu Jun 11 18:31:34 2026
-# Process ID: 884894
-# Current directory: /home/pilipovic/Downloads/FVH/code/vezba10
-# Command line: xsim -nolog -mode tcl -source {xsim.dir/calc_sim/xsim_script.tcl}
-# Log file: 
-# Journal file: /home/pilipovic/Downloads/FVH/code/vezba10/xsim.jou
-# Running On: arch, OS: Linux, CPU Frequency: 1733.838 MHz, CPU Physical cores: 12, Host memory: 16707 MB
-#-----------------------------------------------------------
-source xsim.dir/calc_sim/xsim_script.tcl
-run -all