49 lines
1.7 KiB
Systemverilog
49 lines
1.7 KiB
Systemverilog
/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_if.sv
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DESCRIPTION apb interface
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****************************************************************************/
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`ifndef APB_IF_SV
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`define APB_IF_SV
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/**
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* Interface: apb_if
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*/
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interface apb_if (input logic pclk, input logic presetn);
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parameter ADDR_WIDTH = 32; // up to 32 bits
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parameter RDATA_WIDTH = 32; // up to 32 bits
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parameter WDATA_WIDTH = 32; // up to 32 bits
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parameter SLV_NUM = 15;
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// source is master
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logic [ADDR_WIDTH - 1 : 0] paddr; // the APB address bus
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logic [SLV_NUM - 1 : 0] psel; // select; the slave device is selected
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// and that a data transfer is required
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logic penable; // enable; the second and subsequent
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// cycles of an APB transfer
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logic pwrite; // direction
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logic [WDATA_WIDTH - 1 : 0] pwdata; // write data
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// source is slave
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logic pready; // ready; the slave uses this signal to
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// extend an APB transfer
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logic [RDATA_WIDTH - 1 : 0] prdata; // read data
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logic pslverr; // indicates a transfer failure
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// control
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bit has_checks = 1;
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bit has_coverage = 1;
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// TODO : coverage and assertions go here...
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endinterface : apb_if
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`endif
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