68 lines
2.3 KiB
Systemverilog
68 lines
2.3 KiB
Systemverilog
/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_transaction.sv
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DESCRIPTION sequence item
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****************************************************************************/
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`ifndef I2C_TRANSACTION_SV
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`define I2C_TRANSACTION_SV
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/*
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* Class: i2c_transaction
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*/
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class i2c_transaction extends uvm_sequence_item;
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// fields
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rand i2c_direction_enum dir;
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rand bit [ADDR_WIDTH - 1 : 0] addr;
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rand i2c_ack_enum addr_ack;
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rand bit [DATA_WIDTH - 1 : 0] data;
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rand i2c_ack_enum data_ack;
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// timings (#clk cycles)
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rand int unsigned scl_period; // SCL period
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rand int unsigned start_hold; // start hold time before SCL toggle
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rand int unsigned stop_setup; // setup time from SCL posedge to SDA assert
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rand int unsigned delay; // time between stop and start conditions
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// constraints
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constraint timing_constraint {
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scl_period inside {[1 : 20]};
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scl_period % 4 == 0;
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start_hold inside {[1 : 10]};
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stop_setup inside {[1 : 10]};
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delay inside {[1 : 10]};
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}
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constraint ack_constraint {
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addr_ack dist {I2C_ACK := 8, I2C_NACK := 2};
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data_ack dist {I2C_ACK := 8, I2C_NACK := 2};
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}
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// UVM factory registration
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`uvm_object_utils_begin (i2c_transaction)
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`uvm_field_enum (i2c_direction_enum, dir, UVM_DEFAULT)
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`uvm_field_enum (i2c_ack_enum, data_ack, UVM_DEFAULT)
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`uvm_field_enum (i2c_ack_enum, addr_ack, UVM_DEFAULT)
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`uvm_field_int (addr, UVM_DEFAULT)
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`uvm_field_int (data, UVM_DEFAULT)
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`uvm_field_int (scl_period, UVM_DEFAULT)
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`uvm_field_int (start_hold, UVM_DEFAULT)
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`uvm_field_int (stop_setup, UVM_DEFAULT)
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`uvm_field_int (delay, UVM_DEFAULT)
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`uvm_object_utils_end
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// new - constructor
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function new(string name = "i2c_transaction");
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super.new(name);
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endfunction : new
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endclass : i2c_transaction
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`endif
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