48 lines
1.4 KiB
Systemverilog
48 lines
1.4 KiB
Systemverilog
/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_seq.sv
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DESCRIPTION sequence for assertion reset
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****************************************************************************/
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`ifndef RESET_SEQ_SV
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`define RESET_SEQ_SV
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/**
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* Class: reset_seq
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*/
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class reset_seq extends reset_base_seq;
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// delay before asserting reset (#clk cycles)
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rand int unsigned transmit_del;
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// duration of reset (#clk cycles)
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rand int unsigned duration_time;
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// UVM factory registration
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`uvm_object_utils(reset_seq)
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// constraints
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constraint c_transmit_delay { transmit_del <= 10; }
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constraint c_duration_time { duration_time inside {[1:5]}; }
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// new - constructor
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function new(string name = "reset_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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// send one transaction
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`uvm_do_with(req, { req.duration == duration_time;
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req.transmit_delay == transmit_del; } )
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endtask : body
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endclass : reset_seq
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`endif
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