49 lines
1.5 KiB
Systemverilog
49 lines
1.5 KiB
Systemverilog
/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_transaction.sv
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DESCRIPTION sequence item
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****************************************************************************/
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`ifndef APB_TRANSACTION_SV
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`define APB_TRANSACTION_SV
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/**
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* Class: apb_transaction
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*/
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class apb_transaction extends uvm_sequence_item;
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// fields
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rand bit [ADDR_WIDTH - 1 : 0] addr;
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rand apb_direction_enum dir;
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rand bit [RDATA_WIDTH - 1 : 0] rdata;
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rand bit [WDATA_WIDTH - 1 : 0] wdata;
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rand int unsigned delay = 0;
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bit error;
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// constraints
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constraint c_delay { delay <= 10 ; }
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// UVM factory registration
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`uvm_object_utils_begin(apb_transaction)
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`uvm_field_int(addr, UVM_DEFAULT)
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`uvm_field_enum(apb_direction_enum, dir, UVM_DEFAULT)
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`uvm_field_int(rdata, UVM_DEFAULT)
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`uvm_field_int(wdata, UVM_DEFAULT)
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`uvm_field_int(delay, UVM_DEFAULT)
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`uvm_field_int(error, UVM_DEFAULT)
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`uvm_object_utils_end
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// new - constructor
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function new(string name = "apb_transaction");
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super.new(name);
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endfunction : new
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endclass : apb_transaction
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`endif
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