28 lines
621 B
Verilog
28 lines
621 B
Verilog
// Library: calc1
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// Module: Output Mux
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// Author: Naseer Siddique
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module mux_out(req_data, req_resp, req_data1, req_data2, req_resp1, req_resp2);
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output [0:31] req_data;
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output [0:1] req_resp;
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input [0:31] req_data1, req_data2;
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input [0:1] req_resp1, req_resp2;
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assign req_resp[0:1] =
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(req_resp1[0:1] != 2'b00) ? req_resp1 :
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( req_resp2[0:1] != 2'b00 ) ? req_resp2 :
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2'b00;
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assign req_data[0:31] =
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( req_resp1[0:1] != 2'b00 ) ? req_data1 :
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( req_resp2[0:1] != 2'b00 ) ? req_data2 :
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32'b0;
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endmodule // mux_out
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