156 lines
4.9 KiB
Verilog
156 lines
4.9 KiB
Verilog
// Library: calc1
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// Priority Logic
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// Author: Naseer Siddique
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module priority1 ( prio_alu1_in_cmd, prio_alu1_in_req_id, prio_alu1_out_req_id, prio_alu1_out_vld, prio_alu2_in_cmd, prio_alu2_in_req_id, prio_alu2_out_req_id, prio_alu2_out_vld, c_clk, hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req, local_error_found, reset);
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output [0:3] prio_alu1_in_cmd, prio_alu2_in_cmd;
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output [0:1] prio_alu1_out_req_id, prio_alu1_in_req_id, prio_alu2_in_req_id, prio_alu2_out_req_id;
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output prio_alu1_out_vld, prio_alu2_out_vld;
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input c_clk, local_error_found;
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input [0:3] hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req;
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input [1:7] reset;
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reg [0:3] cmd1, cmd2, cmd3, cmd4;
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reg delay1, delay2;
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wire cmd1_reset, cmd2_reset, cmd3_reset, cmd4_reset;
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reg [0:1] prio_req1_id_q, prio_req2_id_q;
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reg prio_alu1_out_vld_q, prio_alu2_out_vld_q;
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always
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@ (posedge c_clk) begin
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if (reset[1]) begin
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cmd1 <= 0;
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cmd2 <= 0;
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cmd3 <= 0;
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cmd4 <= 0;
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end
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else begin
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fork
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delay1 <= prio_alu1_out_vld_q;
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delay2 <= prio_alu2_out_vld_q;
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cmd1[0:3] <=
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(hold1_prio_req[0:3] != 4'b0) ? hold1_prio_req[0:3] :
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(cmd1_reset) ? 4'b0 :
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cmd1[0:3];
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cmd2[0:3] <=
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(hold2_prio_req[0:3] != 4'b0) ? hold2_prio_req[0:3] :
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(cmd2_reset) ? 4'b0 :
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cmd2[0:3];
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cmd3[0:3] <=
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(hold3_prio_req[0:3] != 4'b0) ? hold3_prio_req[0:3] :
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(cmd3_reset) ? 4'b0 :
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cmd3[0:3];
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cmd4[0:3] <=
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(hold4_prio_req[0:3] != 4'b0) ? hold4_prio_req[0:3] :
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(cmd4_reset) ? 4'b0 :
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cmd4[0:3];
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join
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end
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end // always @ (posedge c_clk)
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always
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@ (delay1 or delay2 or cmd1 or cmd2 or cmd3 or cmd4) begin
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if (delay1)
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prio_alu1_out_vld_q <= 1'b0;
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else if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
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prio_alu1_out_vld_q <= 1'b1;
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else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
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prio_alu1_out_vld_q <= 1'b1;
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else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
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prio_alu1_out_vld_q <= 1'b1;
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else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) && local_error_found )
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prio_alu1_out_vld_q <= 1'b1;
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else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
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prio_alu1_out_vld_q <= 1'b0;
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else prio_alu1_out_vld_q <= 1'b0;
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if (delay2)
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prio_alu2_out_vld_q <= 1'b0;
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else if (cmd1 > 4'b0011)
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prio_alu2_out_vld_q <= 1'b1;
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else if (cmd2 > 4'b0011)
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prio_alu2_out_vld_q <= 1'b1;
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else if (cmd3 > 4'b0011)
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prio_alu2_out_vld_q <= 1'b1;
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else if (cmd4 > 4'b0011)
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prio_alu2_out_vld_q <= 1'b1;
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else prio_alu2_out_vld_q <= 1'b0;
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if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
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prio_req1_id_q[0:1] <= 2'b00;
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else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
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prio_req1_id_q[0:1] <= 2'b01;
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else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
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prio_req1_id_q[0:1] <= 2'b10;
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else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
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prio_req1_id_q[0:1] <= 2'b11;
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else prio_req1_id_q[0:1] <= 2'b00;
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if ( cmd1 > 4'b0011 )
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prio_req2_id_q <= 2'b00;
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else if ( cmd2 > 4'b0011 )
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prio_req2_id_q <= 2'b01;
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else if ( cmd3 > 4'b0011 )
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prio_req2_id_q <= 2'b10;
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else if ( cmd4 > 4'b0011 )
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prio_req2_id_q <= 2'b11;
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else prio_req2_id_q <= 2'b00;
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end // always @ (delay1 or or delay2 or cmd1 or cmd2 or cmd3 or cmd4)
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assign prio_alu1_in_req_id[0:1] = prio_req1_id_q[0:1];
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assign prio_alu2_in_req_id[0:1] = prio_req2_id_q[0:1];
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assign prio_alu1_out_req_id[0:1] = prio_req1_id_q[0:1];
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assign prio_alu2_out_req_id[0:1] = prio_req2_id_q[0:1];
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assign prio_alu1_out_vld = prio_alu1_out_vld_q;
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assign prio_alu2_out_vld = prio_alu2_out_vld_q;
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assign prio_alu1_in_cmd[0:3] =
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(prio_req1_id_q[0:1] == 2'b00) ? cmd1[0:3] :
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(prio_req1_id_q[0:1] == 2'b01) ? cmd2[0:3] :
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(prio_req1_id_q[0:1] == 2'b10) ? cmd3[0:3] :
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(prio_req1_id_q[0:1] == 2'b11) ? cmd4[0:3] :
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4'b0;
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assign prio_alu2_in_cmd[0:3] =
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(prio_req2_id_q[0:1] == 2'b00) ? cmd1[0:3] :
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(prio_req2_id_q[0:1] == 2'b01) ? cmd2[0:3] :
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(prio_req2_id_q[0:1] == 2'b10) ? cmd3[0:3] :
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(prio_req2_id_q[0:1] == 2'b11) ? cmd4[0:3] :
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4'b0;
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assign cmd1_reset =
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(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b00) ) ? 1 :
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(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b00) ) ? 1 :
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0;
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assign cmd2_reset =
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(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b01) ) ? 1 :
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(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b01) ) ? 1 :
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0;
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assign cmd3_reset =
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(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b10) ) ? 1 :
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(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b10) ) ? 1 :
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0;
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assign cmd4_reset =
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(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b11) ) ? 1 :
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(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b11) ) ? 1 :
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0;
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endmodule // priority
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