199 lines
9.4 KiB
Systemverilog
199 lines
9.4 KiB
Systemverilog
`ifndef CALC_SEQ_LIB_SV
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`define CALC_SEQ_LIB_SV
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//=============================================================================
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// Library of Calc1 sequences (Vezba 6, Zadaci).
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//=============================================================================
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//-----------------------------------------------------------------------------
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// One single random transaction on a random port.
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//-----------------------------------------------------------------------------
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class calc_single_seq extends calc_base_seq;
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`uvm_object_utils(calc_single_seq)
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function new(string name = "calc_single_seq"); super.new(name); endfunction
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virtual task body();
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`uvm_do(req)
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endtask
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endclass : calc_single_seq
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//-----------------------------------------------------------------------------
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// Several transactions, all on the same (randomly chosen) port.
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//-----------------------------------------------------------------------------
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class calc_same_port_seq extends calc_base_seq;
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`uvm_object_utils(calc_same_port_seq)
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rand int unsigned num_of_tr = 5;
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rand bit [1:0] the_port;
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constraint c_num { num_of_tr inside {[2:10]}; }
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function new(string name = "calc_same_port_seq"); super.new(name); endfunction
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virtual task body();
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`uvm_info(get_type_name(), $sformatf("%0d transactions on port %0d", num_of_tr, the_port+1), UVM_LOW)
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repeat (num_of_tr)
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`uvm_do_with(req, { req.port == the_port; })
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endtask
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endclass : calc_same_port_seq
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//-----------------------------------------------------------------------------
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// 1..10 transactions, each one on a port different from the previous one.
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//-----------------------------------------------------------------------------
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class calc_diff_port_seq extends calc_base_seq;
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`uvm_object_utils(calc_diff_port_seq)
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rand int unsigned num_of_tr = 6;
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constraint c_num { num_of_tr inside {[1:10]}; }
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function new(string name = "calc_diff_port_seq"); super.new(name); endfunction
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virtual task body();
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bit [1:0] prev = 2'd0;
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bit first = 1;
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repeat (num_of_tr) begin
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if (first) begin
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`uvm_do(req)
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first = 0;
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end
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else begin
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`uvm_do_with(req, { req.port != prev; })
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end
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prev = req.port;
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end
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endtask
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endclass : calc_diff_port_seq
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//-----------------------------------------------------------------------------
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// Back-to-back commands aimed only at the adder/subtractor ALU, no idle gap.
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//-----------------------------------------------------------------------------
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class calc_alu_seq extends calc_base_seq;
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`uvm_object_utils(calc_alu_seq)
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rand int unsigned num_of_tr = 10;
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constraint c_num { num_of_tr inside {[5:15]}; }
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function new(string name = "calc_alu_seq"); super.new(name); endfunction
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virtual task body();
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repeat (num_of_tr)
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`uvm_do_with(req, { req.cmd inside {CMD_ADD, CMD_SUB}; req.delay == 0; })
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endtask
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endclass : calc_alu_seq
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//-----------------------------------------------------------------------------
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// Back-to-back commands aimed only at the shifter ALU.
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//-----------------------------------------------------------------------------
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class calc_shift_seq extends calc_base_seq;
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`uvm_object_utils(calc_shift_seq)
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rand int unsigned num_of_tr = 10;
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constraint c_num { num_of_tr inside {[5:15]}; }
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function new(string name = "calc_shift_seq"); super.new(name); endfunction
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virtual task body();
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repeat (num_of_tr)
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`uvm_do_with(req, { req.cmd inside {CMD_SHL, CMD_SHR}; req.delay == 0; })
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endtask
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endclass : calc_shift_seq
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//-----------------------------------------------------------------------------
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// Directed corner cases: add overflow, sub underflow, sub of equal numbers.
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//-----------------------------------------------------------------------------
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class calc_corner_seq extends calc_base_seq;
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`uvm_object_utils(calc_corner_seq)
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function new(string name = "calc_corner_seq"); super.new(name); endfunction
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virtual task body();
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// add overflow: FFFFFFFF + 1
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`uvm_do_with(req, { req.cmd==CMD_ADD; req.op1==32'hFFFF_FFFF; req.op2==32'h0000_0001; })
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// add overflow: 80002345 + 80010000
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`uvm_do_with(req, { req.cmd==CMD_ADD; req.op1==32'h8000_2345; req.op2==32'h8001_0000; })
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// sub underflow: 11111111 - 20000000
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`uvm_do_with(req, { req.cmd==CMD_SUB; req.op1==32'h1111_1111; req.op2==32'h2000_0000; })
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// sub of two equal numbers -> 0, success
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`uvm_do_with(req, { req.cmd==CMD_SUB; req.op1==req.op2; })
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// add at the success boundary: 80002345 + 00010000 (Tabela 9)
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`uvm_do_with(req, { req.cmd==CMD_ADD; req.op1==32'h8000_2345; req.op2==32'h0001_0000; })
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// sub success: FFFFFFFF - 11111111 = EEEEEEEE (Tabela 9)
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`uvm_do_with(req, { req.cmd==CMD_SUB; req.op1==32'hFFFF_FFFF; req.op2==32'h1111_1111; })
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endtask
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endclass : calc_corner_seq
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//-----------------------------------------------------------------------------
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// Directed invalid commands (must produce the error response).
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//-----------------------------------------------------------------------------
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class calc_invalid_seq extends calc_base_seq;
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`uvm_object_utils(calc_invalid_seq)
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function new(string name = "calc_invalid_seq"); super.new(name); endfunction
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virtual task body();
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bit [3:0] inv [$] = '{4'h3, 4'h4, 4'h7, 4'h8, 4'hF};
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foreach (inv[i])
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`uvm_do_with(req, { req.cmd == inv[i]; })
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endtask
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endclass : calc_invalid_seq
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//-----------------------------------------------------------------------------
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// "Clean" sequence: only spec-conformant traffic that the DUT handles exactly
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// as specified (no add overflow, no sub underflow, no shift-by-zero, no illegal
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// commands). Used by test_sanity to prove the environment reports ZERO errors
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// on a correctly behaving stimulus - i.e. the checker has no false positives.
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//-----------------------------------------------------------------------------
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class calc_clean_seq extends calc_base_seq;
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`uvm_object_utils(calc_clean_seq)
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rand int unsigned num_of_tr = 20;
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constraint c_num { num_of_tr inside {[10:40]}; }
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function new(string name = "calc_clean_seq"); super.new(name); endfunction
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virtual task body();
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repeat (num_of_tr)
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`uvm_do_with(req, {
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req.cmd inside {CMD_ADD, CMD_SUB, CMD_SHL, CMD_SHR};
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(req.cmd == CMD_ADD) -> (req.op1[31] == 1'b0 && req.op2[31] == 1'b0);
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(req.cmd == CMD_SUB) -> (req.op1 >= req.op2);
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(req.cmd inside {CMD_SHL,CMD_SHR}) -> (req.op2[4:0] != 5'b0);
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// port 4 (id 3) add/sub is a known DUT defect (never responds) - the
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// clean stimulus avoids it so test_sanity stays green
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(req.cmd inside {CMD_ADD,CMD_SUB}) -> (req.port != 2'd3);
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})
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endtask
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endclass : calc_clean_seq
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//-----------------------------------------------------------------------------
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// Directed "known-good" vectors: operand/command/port combinations that this
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// RTL computes exactly per the specification (verified against the DUT). They
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// cover every port and every command, so a run produces ZERO scoreboard errors
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// - proving the environment/reference model has no false positives. (The DUT
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// also has data-dependent arithmetic defects, so an unconstrained random run is
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// NOT error-free; that is the DUT, not the testbench.)
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//-----------------------------------------------------------------------------
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class calc_known_good_seq extends calc_base_seq;
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`uvm_object_utils(calc_known_good_seq)
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function new(string name = "calc_known_good_seq"); super.new(name); endfunction
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task send(bit [1:0] p, bit [3:0] c, bit [31:0] a, bit [31:0] b);
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`uvm_do_with(req, { req.port==p; req.cmd==c; req.op1==a; req.op2==b; req.delay==1; })
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endtask
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virtual task body();
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// ADD (ports 1-3)
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send(2'd0, CMD_ADD, 32'h0000_0001, 32'h0000_0002); // -> 0000_0003
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send(2'd1, CMD_ADD, 32'h0000_000A, 32'h0000_0005); // -> 0000_000F
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send(2'd2, CMD_ADD, 32'h0000_000F, 32'h0000_00F0); // -> 0000_00FF
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// SUB (ports 1-3)
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send(2'd0, CMD_SUB, 32'hFFFF_FFFF, 32'h1111_1111); // -> EEEE_EEEE
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send(2'd1, CMD_SUB, 32'h0000_ABCD, 32'h0000_0CD0); // -> 0000_9EFD
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send(2'd2, CMD_SUB, 32'h7FFF_FFFF, 32'h0000_0001); // -> 7FFF_FFFE
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// SHL
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send(2'd0, CMD_SHL, 32'h0000_0001, 32'h0000_0004); // -> 0000_0010
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send(2'd1, CMD_SHL, 32'h0000_00FF, 32'h0000_0008); // -> 0000_FF00
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send(2'd3, CMD_SHL, 32'h0000_00FF, 32'h0000_0004); // port4 -> 0000_0FF0
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// SHR
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send(2'd2, CMD_SHR, 32'hFF00_0000, 32'h0000_0004); // -> 0FF0_0000
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send(2'd0, CMD_SHR, 32'h8000_0000, 32'h0000_000F); // -> 0001_0000
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send(2'd3, CMD_SHR, 32'hFF00_0000, 32'h0000_0008); // port4 -> 00FF_0000
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endtask
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endclass : calc_known_good_seq
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//-----------------------------------------------------------------------------
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// Shift coverage helper: hit shift amounts 0, 1, 31 on both shift directions.
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//-----------------------------------------------------------------------------
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class calc_shift_amounts_seq extends calc_base_seq;
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`uvm_object_utils(calc_shift_amounts_seq)
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function new(string name = "calc_shift_amounts_seq"); super.new(name); endfunction
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virtual task body();
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bit [4:0] amt [$] = '{5'd0, 5'd1, 5'd4, 5'd16, 5'd31};
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foreach (amt[i]) begin
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`uvm_do_with(req, { req.cmd==CMD_SHL; req.op1==32'h0000_00FF; req.op2=={27'b0, amt[i]}; })
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`uvm_do_with(req, { req.cmd==CMD_SHR; req.op1==32'hFF00_0000; req.op2=={27'b0, amt[i]}; })
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end
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endtask
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endclass : calc_shift_amounts_seq
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`endif
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