30 lines
932 B
Systemverilog
30 lines
932 B
Systemverilog
`ifndef CALC_IF_SV
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`define CALC_IF_SV
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interface calc_if (input clk, logic [6 : 0] rst);
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parameter DATA_WIDTH = 32;
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parameter RESP_WIDTH = 2;
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parameter CMD_WIDTH = 4;
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logic [DATA_WIDTH - 1 : 0] out_data1;
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logic [DATA_WIDTH - 1 : 0] out_data2;
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logic [DATA_WIDTH - 1 : 0] out_data3;
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logic [DATA_WIDTH - 1 : 0] out_data4;
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logic [RESP_WIDTH - 1 : 0] out_resp1;
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logic [RESP_WIDTH - 1 : 0] out_resp2;
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logic [RESP_WIDTH - 1 : 0] out_resp3;
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logic [RESP_WIDTH - 1 : 0] out_resp4;
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logic [CMD_WIDTH - 1 : 0] req1_cmd_in;
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logic [DATA_WIDTH - 1 : 0] req1_data_in;
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logic [CMD_WIDTH - 1 : 0] req2_cmd_in;
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logic [DATA_WIDTH - 1 : 0] req2_data_in;
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logic [CMD_WIDTH - 1 : 0] req3_cmd_in;
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logic [DATA_WIDTH - 1 : 0] req3_data_in;
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logic [CMD_WIDTH - 1 : 0] req4_cmd_in;
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logic [DATA_WIDTH - 1 : 0] req4_data_in;
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endinterface : calc_if
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`endif
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