41 lines
940 B
Systemverilog
41 lines
940 B
Systemverilog
/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_if.sv
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DESCRIPTION i2c interface
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****************************************************************************/
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`ifndef I2C_IF_SV
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`define I2C_IF_SV
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/*
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* Interface: i2c_if
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*/
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interface i2c_if(input logic clk, input logic rst);
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// connected to DUT
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wire sda_wire;
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wire scl_wire;
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// driven by uvc
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logic sda;
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logic scl;
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assign sda_wire = sda;
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assign scl_wire = scl;
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// control
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bit has_checks = 1;
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bit has_coverage = 1;
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// TODO : coverage and assertions go here...
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endinterface : i2c_if
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`endif
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