init
This commit is contained in:
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_base_seq.sv
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DESCRIPTION base sequence to be extended by other sequences
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****************************************************************************/
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`ifndef APB_MASTER_BASE_SEQ_SV
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`define APB_MASTER_BASE_SEQ_SV
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/**
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* Class: apb_master_base_seq
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*/
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class apb_master_base_seq extends uvm_sequence #(apb_transaction, apb_transaction);
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// p_sequencer for APB master sequences
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`uvm_declare_p_sequencer(apb_master_sequencer)
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// UVM factory registration
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`uvm_object_utils(apb_master_base_seq)
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// new - constructor
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function new(string name = "apb_master_base_seq");
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super.new(name);
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endfunction : new
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endclass : apb_master_base_seq
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_read_after_write_seq.sv
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DESCRIPTION sequence for writing and reading from one address
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****************************************************************************/
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`ifndef APB_MASTER_READ_AFTER_WRITE_SEQ_SV
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`define APB_MASTER_READ_AFTER_WRITE_SEQ_SV
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/**
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* Class: apb_master_read_after_write_seq
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*/
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class apb_master_read_after_write_seq extends apb_master_base_seq;
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rand int unsigned delay; // transaction delay
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rand bit [ADDR_WIDTH - 1 : 0] addr; // address to write/read
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// constraints
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constraint delay_cst { delay inside {[1 : 10]};}
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// UVM factory registration
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`uvm_object_utils(apb_master_read_after_write_seq)
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// new - constructor
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function new(string name = "apb_master_read_after_write_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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// write
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`uvm_do_with( req,
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{req.addr == addr;
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req.dir == APB_READ;
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req.delay == delay;})
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// read
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`uvm_do_with( req,
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{req.addr == addr;
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req.dir == APB_READ;
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req.delay == delay;})
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endtask : body
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endclass : apb_master_read_after_write_seq
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_read_all_seq.sv
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DESCRIPTION sequence for reading from all valid addresses
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****************************************************************************/
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`ifndef APB_MASTER_READ_ALL_SEQ_SV
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`define APB_MASTER_READ_ALL_SEQ_SV
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/**
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* Class: apb_master_read_all_seq
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*/
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class apb_master_read_all_seq extends apb_master_base_seq;
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// UVM factory registration
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`uvm_object_utils(apb_master_read_all_seq)
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// new - constructor
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function new(string name = "apb_master_read_all_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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bit [ADDR_WIDTH - 1 : 0] end_addr, curr_addr;
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// read from all addresses in all slaves
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foreach (p_sequencer.cfg.slave_cfg_queue[i]) begin
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curr_addr = p_sequencer.cfg.slave_cfg_queue[i].start_address;
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end_addr = p_sequencer.cfg.slave_cfg_queue[i].end_address;
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while (curr_addr != end_addr) begin
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`uvm_do_with( req, {
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req.addr == curr_addr;
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req.dir == APB_READ;})
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curr_addr++;
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end
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end
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endtask : body
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endclass : apb_master_read_all_seq
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_read_seq.sv
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DESCRIPTION sequence for reading from one address
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****************************************************************************/
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`ifndef APB_MASTER_READ_SEQ_SV
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`define APB_MASTER_READ_SEQ_SV
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/**
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* Class: apb_master_read_seq
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*/
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class apb_master_read_seq extends apb_master_base_seq;
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rand int unsigned delay; // transaction delay
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rand bit [ADDR_WIDTH - 1 : 0] addr; // address to read
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// constraints
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constraint delay_cst { delay inside {[1 : 10]};}
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// UVM factory registration
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`uvm_object_utils(apb_master_read_seq)
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// new - constructor
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function new(string name = "apb_master_read_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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`uvm_do_with( req,
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{req.addr == addr;
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req.dir == APB_READ;
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req.delay == delay;})
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endtask : body
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endclass : apb_master_read_seq
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`endif
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@@ -0,0 +1,23 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_seq_lib.sv
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DESCRIPTION sequence includes
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****************************************************************************/
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`ifndef APB_MASTER_SEQ_LIB_SV
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`define APB_MASTER_SEQ_LIB_SV
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`include "master/sequences/apb_master_base_seq.sv"
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`include "master/sequences/apb_master_simple_seq.sv"
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`include "master/sequences/apb_master_read_seq.sv"
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`include "master/sequences/apb_master_write_seq.sv"
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`include "master/sequences/apb_master_read_all_seq.sv"
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`include "master/sequences/apb_master_write_all_seq.sv"
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`include "master/sequences/apb_master_read_after_write_seq.sv"
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_simple_seq.sv
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DESCRIPTION simple sequence; random transactions
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****************************************************************************/
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`ifndef APB_MASTER_SIMPLE_SEQ_SV
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`define APB_MASTER_SIMPLE_SEQ_SV
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/**
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* Class: apb_master_simple_seq
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*/
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class apb_master_simple_seq extends apb_master_base_seq;
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rand int unsigned num_of_tr;
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// constraints
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constraint num_of_tr_cst { num_of_tr inside {[1 : 10]};}
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// UVM factory registration
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`uvm_object_utils(apb_master_simple_seq)
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// new - constructor
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function new(string name = "apb_master_simple_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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repeat(num_of_tr) begin
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`uvm_do(req)
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end
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endtask : body
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endclass : apb_master_simple_seq
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_write_all_seq.sv
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DESCRIPTION sequence for writing to all valid addresses
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****************************************************************************/
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`ifndef APB_MASTER_WRITE_ALL_SEQ_SV
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`define APB_MASTER_WRITE_ALL_SEQ_SV
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/**
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* Class: apb_master_write_all_seq
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*/
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class apb_master_write_all_seq extends apb_master_base_seq;
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bit data_is_rand = 1; // 1 = data will be randomly chosen for every write
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// 0 = used data from "data_to_write" field
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bit [WDATA_WIDTH - 1 : 0] data_to_write;
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rand bit [WDATA_WIDTH - 1 : 0] data;
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// UVM factory registration
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`uvm_object_utils(apb_master_write_all_seq)
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// new - constructor
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function new(string name = "apb_master_write_all_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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bit [ADDR_WIDTH - 1 : 0] end_addr, curr_addr;
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// write to all addresses in all slaves
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foreach (p_sequencer.cfg.slave_cfg_queue[i]) begin
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curr_addr = p_sequencer.cfg.slave_cfg_queue[i].start_address;
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end_addr = p_sequencer.cfg.slave_cfg_queue[i].end_address;
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while (curr_addr != end_addr) begin
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if (data_is_rand) begin
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assert(this.randomize());
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end
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else begin
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data = data_to_write;
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end
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`uvm_do_with( req, {
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req.addr == curr_addr;
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req.wdata == data;
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req.dir == APB_WRITE;})
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curr_addr++;
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end
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end
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endtask : body
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endclass : apb_master_write_all_seq
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`endif
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@@ -0,0 +1,47 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE apb_master_write_seq.sv
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DESCRIPTION sequence for writing to one address
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****************************************************************************/
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`ifndef APB_MASTER_WRITE_SEQ_SV
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`define APB_MASTER_WRITE_SEQ_SV
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/**
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* Class: apb_master_write_seq
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*/
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class apb_master_write_seq extends apb_master_base_seq;
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rand int unsigned delay; // transaction delay
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rand bit [ADDR_WIDTH - 1 : 0] addr; // address to write
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rand bit [WDATA_WIDTH - 1 : 0] data; // data to write
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// constraints
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constraint delay_cst { delay inside {[1 : 10]};}
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// UVM factory registration
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`uvm_object_utils(apb_master_write_seq)
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// new - constructor
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function new(string name = "apb_master_write_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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`uvm_do_with( req, {
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req.addr == addr;
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req.dir == APB_WRITE;
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req.wdata == data;
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req.delay == delay;})
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endtask : body
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endclass : apb_master_write_seq
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`endif
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