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This commit is contained in:
Nebojša Pilipović
2026-06-12 07:53:32 +02:00
commit 59e71f3297
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30
code/Vezba 13 - prateci materijal/i2c_uvc/examples/dut.sv Normal file
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE dut.sv
DESCRIPTION
****************************************************************************/
`ifndef DUT_SV
`define DUT_SV
/**
* Module: dut
*/
module dut#(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8
)
(
input logic clk,
input logic rst,
ref logic sda,
ref logic scl
);
endmodule : dut
`endif

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code/Vezba 13 - prateci materijal/i2c_uvc/examples/i2c_test_top.sv Normal file
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE i2c_test_top.sv
DESCRIPTION top module
- connects DUT and interface
- generates clk and reset
- runs UVM test
****************************************************************************/
`ifndef I2C_TEST_TOP_SV
`define I2C_TEST_TOP_SV
/**
* Module: i2c_test_top
*/
module i2c_test_top;
import uvm_pkg::*; // import the UVM library
`include "uvm_macros.svh" // Include the UVM macros
import i2c_pkg::*; // import the i2c pkg
`include "i2c_test_lib.sv"
`include "dut.sv"
logic clock;
logic reset;
// interface
i2c_if i2c_vif(clock, reset);
// DUT
dut #( .ADDR_WIDTH(7),
.DATA_WIDTH(8)
) dut_inst (
.clk (clock),
.rst (reset),
.scl (i2c_vif.scl),
.sda (i2c_vif.sda)
);
// set interface in db; run UVM test
initial begin
uvm_config_db#(virtual i2c_if)::set(null,"uvm_test_top.*","i2c_if", i2c_vif);
run_test();
end
// initialize clock and reset
initial begin
clock <= 1'b0;
reset <= 1'b1;
#50 reset <= 1'b0;
end
// generate clock
always #5 clock = ~clock;
endmodule : i2c_test_top
`endif

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code/Vezba 13 - prateci materijal/i2c_uvc/examples/tests/i2c_test_base.sv Normal file
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE i2c_test_base.sv
DESCRIPTION base test to be extended by other tests
****************************************************************************/
`ifndef I2C_TEST_BASE_SV
`define I2C_TEST_BASE_SV
/**
* Class: i2c_test_base
*/
class i2c_test_base extends uvm_test;
// UVM factory registration
`uvm_component_utils (i2c_test_base)
// main environment
i2c_env env;
// new - constructor
function new(string name = "i2c_test_base", uvm_component parent = null);
super.new(name, parent);
endfunction : new
// UVM build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// build environment
env = i2c_env::type_id::create("env", this);
endfunction : build_phase
// UVM end_of_elaboration_phase
function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
// display verification environment topology
uvm_top.print_topology();
endfunction : end_of_elaboration_phase
endclass : i2c_test_base
`endif

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code/Vezba 13 - prateci materijal/i2c_uvc/examples/tests/i2c_test_lib.sv Normal file
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE i2c_test_lib.sv
DESCRIPTION test includes
****************************************************************************/
`ifndef I2C_TEST_LIB_SV
`define I2C_TEST_LIB_SV
`include "i2c_test_base.sv"
`include "i2c_test_simple.sv"
`endif

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code/Vezba 13 - prateci materijal/i2c_uvc/examples/tests/i2c_test_simple.sv Normal file
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE i2c_test_simple.sv
DESCRIPTION simple test for debug
****************************************************************************/
`ifndef I2C_TEST_SIMPLE_SV
`define I2C_TEST_SIMPLE_SV
/**
* Class: i2c_test_simple
*/
class i2c_test_simple extends i2c_test_base;
// UVM factory registration
`uvm_component_utils (i2c_test_simple)
// sequences
i2c_master_simple_seq master_seq;
i2c_slave_simple_seq slave_seq;
// new - constructor
function new(string name = "i2c_test_simple", uvm_component parent = null);
super.new(name, parent);
endfunction : new
// UVM build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// build all sequences
master_seq = i2c_master_simple_seq::type_id::create("master_seq");
slave_seq = i2c_slave_simple_seq::type_id::create("slave_seq");
endfunction : build_phase
// UVM run_phase
task run_phase(uvm_phase phase);
assert(master_seq.randomize()); // random fields in master seq.
phase.raise_objection(this); // test cannot end yet
// start all sequences
fork
master_seq.start(env.master.seqr);
slave_seq.start(env.slave.seqr); // runs forever
join_any
// only way to get here is if master sequence finished
phase.drop_objection(this); // test can end
endtask : run_phase
endclass : i2c_test_simple
`endif