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code/Vezba 13 - prateci materijal/i2c_uvc/examples/i2c_test_top.sv

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+/****************************************************************************
+    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
+    |F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
+    +-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
+
+    FILE            i2c_test_top.sv
+
+    DESCRIPTION     top module
+                    - connects DUT and interface
+                    - generates clk and reset
+                    - runs UVM test
+
+ ****************************************************************************/
+
+`ifndef I2C_TEST_TOP_SV
+`define I2C_TEST_TOP_SV
+
+/**
+ * Module: i2c_test_top
+ */
+module i2c_test_top;
+
+    import uvm_pkg::*;            // import the UVM library
+    `include "uvm_macros.svh"     // Include the UVM macros
+
+    import i2c_pkg::*;            // import the i2c pkg
+    
+    `include "i2c_test_lib.sv"
+    
+    `include "dut.sv"
+
+    logic clock;
+    logic reset;
+
+    // interface
+    i2c_if i2c_vif(clock, reset);
+    
+    // DUT
+    dut #(  .ADDR_WIDTH(7),
+            .DATA_WIDTH(8)
+        ) dut_inst (
+            .clk    (clock),
+            .rst    (reset),
+            .scl    (i2c_vif.scl),
+            .sda    (i2c_vif.sda)
+        );    
+
+    // set interface in db; run UVM test
+    initial begin
+        uvm_config_db#(virtual i2c_if)::set(null,"uvm_test_top.*","i2c_if", i2c_vif);
+        run_test();
+    end
+    
+    // initialize clock and reset
+    initial begin
+        clock <= 1'b0;
+        reset <= 1'b1;
+        #50 reset <= 1'b0;
+    end
+
+    // generate clock
+    always #5 clock = ~clock;    
+
+endmodule : i2c_test_top
+
+`endif
+