init
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_master_base_seq.sv
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DESCRIPTION base sequence to be extended by other sequences
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****************************************************************************/
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`ifndef I2C_MASTER_BASE_SEQ_SV
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`define I2C_MASTER_BASE_SEQ_SV
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/*
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* Class: i2c_master_base_seq
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*/
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class i2c_master_base_seq extends uvm_sequence #(i2c_transaction);
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// UVM factory registration
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`uvm_object_utils(i2c_master_base_seq)
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// new - constructor
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function new(string name = "i2c_master_base_seq");
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super.new(name);
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endfunction: new
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endclass: i2c_master_base_seq
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`endif
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_master_seq_lib.sv
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DESCRIPTION sequence includes
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****************************************************************************/
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`ifndef I2C_MASTER_SEQ_LIB_SV
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`define I2C_MASTER_SEQ_LIB_SV
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`include "master/sequences/i2c_master_base_seq.sv"
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`include "master/sequences/i2c_master_simple_seq.sv"
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`endif
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@@ -0,0 +1,42 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE i2c_master_simple_seq.sv
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DESCRIPTION simple sequence; random transactions
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****************************************************************************/
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`ifndef I2C_MASTER_SIMPLE_SEQ_SV
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`define I2C_MASTER_SIMPLE_SEQ_SV
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/**
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* Class: i2c_master_simple_seq
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*/
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class i2c_master_simple_seq extends i2c_master_base_seq;
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rand int unsigned num_of_tr;
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// constraints
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constraint num_of_tr_cst { num_of_tr inside {[1 : 10]};}
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// UVM factory registration
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`uvm_object_utils(i2c_master_simple_seq)
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// new - constructor
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function new(string name = "i2c_master_simple_seq");
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super.new(name);
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endfunction : new
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// sequence generation logic in body
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virtual task body();
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repeat(num_of_tr) begin
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`uvm_do(req)
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end
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endtask : body
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endclass : i2c_master_simple_seq
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`endif
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