init

code/vezba1/v1_build_file.f

@@ -0,0 +1,5 @@
+      v1_counter.sv
+      v1_simple_tb.sv
+      -gui
+      -access +rwc
+      

code/vezba1/v1_counter.sv

@@ -0,0 +1,26 @@
+module counter
+  (input clk,
+   input rst,
+   input ce_i,
+   input up_i,
+   output logic [3:0] q_o);
+
+  logic [3:0] count;
+
+  always_ff @(posedge clk) begin
+    if (rst) begin
+      count <= 4'b0000;
+    end
+    else if(ce_i) begin
+      if(up_i) begin
+        count <= count + 1'b1;
+      end
+      else begin
+        count <= count - 1'b1;
+      end
+    end
+  end
+
+  assign q_o = count;
+
+endmodule : counter

code/vezba1/v1_simple_tb.sv

@@ -0,0 +1,47 @@
+module simple_tb;
+
+  logic clk;
+  logic rst;
+  logic ce;
+  logic up;
+  logic [3 : 0] data;
+
+  counter cnt_inst (clk, rst, ce, up, data);
+
+  function void compare_values(logic [3:0] expected, logic [3 : 0] received);
+    if(expected !== received) begin
+      $error("Error in comparison: expected %0h, received %0h\n", expected, received);
+    end
+    else begin
+      $display("Successful comparison at time %0t with value %0h", $time, expected);
+    end
+  endfunction : compare_values
+
+  initial begin
+    $display("Starting simulation...");
+    #500ns;
+    $finish;
+  end
+
+  initial begin
+    repeat(3) @(posedge clk iff !rst);
+    compare_values('he, data);
+  end
+
+  initial begin
+    clk <= 0;
+    rst <= 1;
+    up <= 0;
+    ce <= 1;
+    #50ns rst <= 0;
+  end
+
+  always begin
+    #5ns clk <= ~clk;
+  end
+
+  final begin
+    $display("Ending simulation at time %0t", $time);
+  end
+
+endmodule : simple_tb