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2026-06-12 07:53:32 +02:00
commit 59e71f3297
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code/vezba1/v1_counter.sv Normal file
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module counter
(input clk,
input rst,
input ce_i,
input up_i,
output logic [3:0] q_o);
logic [3:0] count;
always_ff @(posedge clk) begin
if (rst) begin
count <= 4'b0000;
end
else if(ce_i) begin
if(up_i) begin
count <= count + 1'b1;
end
else begin
count <= count - 1'b1;
end
end
end
assign q_o = count;
endmodule : counter