init

code/vezba10/verif/Agent/calc_agent.sv

@@ -0,0 +1,47 @@
+class calc_agent extends uvm_agent;
+
+   // components
+   calc_driver drv;
+   calc_sequencer seqr;
+   calc_monitor mon;
+   virtual interface calc_if vif;
+   // configuration
+   calc_config cfg;
+   int value;   
+   `uvm_component_utils_begin (calc_agent)
+      `uvm_field_object(cfg, UVM_DEFAULT)
+   `uvm_component_utils_end
+
+   function new(string name = "calc_agent", uvm_component parent = null);
+      super.new(name,parent);
+   endfunction
+
+   function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      /************Geting from configuration database*******************/
+      if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
+        `uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
+      
+      if(!uvm_config_db#(calc_config)::get(this, "", "calc_config", cfg))
+        `uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
+      /*****************************************************************/
+      
+      /************Setting to configuration database********************/
+            uvm_config_db#(virtual calc_if)::set(this, "*", "calc_if", vif);
+      /*****************************************************************/
+      
+      mon = calc_monitor::type_id::create("mon", this);
+      if(cfg.is_active == UVM_ACTIVE) begin
+         drv = calc_driver::type_id::create("drv", this);
+         seqr = calc_sequencer::type_id::create("seqr", this);
+      end
+   endfunction : build_phase
+
+   function void connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if(cfg.is_active == UVM_ACTIVE) begin
+         drv.seq_item_port.connect(seqr.seq_item_export);
+      end
+   endfunction : connect_phase
+
+endclass : calc_agent

code/vezba10/verif/Agent/calc_agent_pkg.sv

@@ -0,0 +1,25 @@
+`ifndef CALC_AGENT_PKG
+`define CALC_AGENT_PKG
+
+package calc_agent_pkg;
+ 
+   import uvm_pkg::*;
+   `include "uvm_macros.svh"
+
+   //////////////////////////////////////////////////////////
+   // include Agent components : driver,monitor,sequencer
+   /////////////////////////////////////////////////////////
+   import configurations_pkg::*;   
+   
+   `include "calc_seq_item.sv"
+   `include "calc_sequencer.sv"
+   `include "calc_driver.sv"
+   `include "calc_monitor.sv"
+   `include "calc_agent.sv"
+
+endpackage
+
+`endif
+
+
+

code/vezba10/verif/Agent/calc_driver.sv

@@ -0,0 +1,115 @@
+`ifndef CALC_DRIVER_SV
+ `define CALC_DRIVER_SV
+
+//-----------------------------------------------------------------------------
+// Calc1 driver.
+//
+// Protocol (Vezba 5):
+//   * command + operand1 are driven in the same cycle,
+//   * operand2 is driven in the next cycle (command line back to 0),
+//   * a response appears on out_respX a few (>=3) cycles later.
+//
+// Only one request may be outstanding per port, so after issuing a request the
+// driver waits for that port's response before completing the item.  This keeps
+// the very simple "bidirectional, non-pipelined" use model from Vezba 6.
+//-----------------------------------------------------------------------------
+class calc_driver extends uvm_driver#(calc_seq_item);
+
+   `uvm_component_utils(calc_driver)
+
+   virtual interface calc_if vif;
+
+   function new(string name = "calc_driver", uvm_component parent = null);
+      super.new(name,parent);
+   endfunction
+
+   function void connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
+        `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
+   endfunction : connect_phase
+
+   task main_phase(uvm_phase phase);
+      // start from a known idle state and wait until reset is released
+      reset_inputs();
+      wait_reset_done();
+
+      forever begin
+         seq_item_port.get_next_item(req);
+         `uvm_info(get_type_name(),
+                   $sformatf("Driving: %s", req.convert2string()), UVM_HIGH)
+         drive_item(req);
+         seq_item_port.item_done();
+      end
+   endtask : main_phase
+
+   // Drive a single transaction following the two-cycle request protocol and
+   // wait for the corresponding response on the same port.
+   task drive_item(calc_seq_item it);
+      int unsigned wait_cnt;
+
+      // optional idle gap before the request
+      repeat (it.delay) @(posedge vif.clk);
+
+      // cycle 1: command + operand1
+      drive_req(it.port, it.cmd, it.op1);
+      @(posedge vif.clk);
+
+      // cycle 2: operand2, command de-asserted
+      drive_req(it.port, CMD_NOP, it.op2);
+      @(posedge vif.clk);
+
+      // idle the port again while the pipeline produces the result
+      drive_req(it.port, CMD_NOP, '0);
+
+      // wait for this port's response (resp != 0), bounded so a non-responding
+      // DUT cannot deadlock the test
+      wait_cnt = 0;
+      do begin
+         @(posedge vif.clk);
+         wait_cnt++;
+      end while (get_resp(it.port) === RESP_NONE && wait_cnt < RSP_TIMEOUT);
+
+      if (get_resp(it.port) === RESP_NONE)
+        `uvm_warning(get_type_name(),
+                     $sformatf("No response on port %0d within %0d cycles (cmd=%s) - the scoreboard will flag this",
+                               it.port+1, RSP_TIMEOUT, it.cmd2string()))
+   endtask : drive_item
+
+   // Drive command/data onto the selected port, leaving the others untouched.
+   task drive_req(bit [1:0] port, bit [CMD_WIDTH-1:0] cmd, bit [DATA_WIDTH-1:0] data);
+      case (port)
+        2'd0 : begin vif.req1_cmd_in <= cmd; vif.req1_data_in <= data; end
+        2'd1 : begin vif.req2_cmd_in <= cmd; vif.req2_data_in <= data; end
+        2'd2 : begin vif.req3_cmd_in <= cmd; vif.req3_data_in <= data; end
+        2'd3 : begin vif.req4_cmd_in <= cmd; vif.req4_data_in <= data; end
+      endcase
+   endtask : drive_req
+
+   // Combinational read of a port's response line.
+   function bit [RESP_WIDTH-1:0] get_resp(bit [1:0] port);
+      case (port)
+        2'd0 : return vif.out_resp1;
+        2'd1 : return vif.out_resp2;
+        2'd2 : return vif.out_resp3;
+        2'd3 : return vif.out_resp4;
+      endcase
+   endfunction
+
+   // Drive all request lines to their idle (zero) state.
+   task reset_inputs();
+      vif.req1_cmd_in <= '0; vif.req1_data_in <= '0;
+      vif.req2_cmd_in <= '0; vif.req2_data_in <= '0;
+      vif.req3_cmd_in <= '0; vif.req3_data_in <= '0;
+      vif.req4_cmd_in <= '0; vif.req4_data_in <= '0;
+   endtask : reset_inputs
+
+   task wait_reset_done();
+      // reset is active-high (all ones); wait until it is fully released
+      while (vif.rst !== '0) @(posedge vif.clk);
+      `uvm_info(get_type_name(), "Reset released - starting to drive", UVM_LOW)
+   endtask : wait_reset_done
+
+endclass : calc_driver
+
+`endif

code/vezba10/verif/Agent/calc_monitor.sv

@@ -0,0 +1,206 @@
+`ifndef CALC_MONITOR_SV
+ `define CALC_MONITOR_SV
+
+//-----------------------------------------------------------------------------
+// Calc1 monitor.
+//
+// Passive component.  One collector thread per port reconstructs a transaction
+// from the pin activity:
+//   * a request starts when reqX_cmd_in != 0  -> capture cmd and operand1,
+//   * operand2 is the data line on the following cycle,
+//   * the matching response is the first cycle in which out_respX != 0.
+//
+// The completed transaction (stimulus + observed response/result) is broadcast
+// over the analysis port to the scoreboard, and functional coverage is sampled.
+//-----------------------------------------------------------------------------
+class calc_monitor extends uvm_monitor;
+
+   // control fields
+   bit checks_enable   = 1;
+   bit coverage_enable = 1;
+
+   uvm_analysis_port #(calc_seq_item) item_collected_port;
+
+   `uvm_component_utils_begin(calc_monitor)
+      `uvm_field_int(checks_enable,   UVM_DEFAULT)
+      `uvm_field_int(coverage_enable, UVM_DEFAULT)
+   `uvm_component_utils_end
+
+   // The virtual interface used to view HDL signals.
+   virtual interface calc_if vif;
+
+   // number of transactions collected (per port and total)
+   int unsigned num_collected;
+
+   //--------------------------------------------------------------------------
+   // Functional coverage model (Vezba 11).
+   //--------------------------------------------------------------------------
+   bit [CMD_WIDTH-1:0]  cov_cmd;
+   bit [1:0]            cov_port;
+   bit [RESP_WIDTH-1:0] cov_resp;
+   bit [DATA_WIDTH-1:0] cov_op1;
+   bit [DATA_WIDTH-1:0] cov_op2;
+
+   covergroup calc_cg;
+      option.per_instance = 1;
+      option.name         = "calc_functional_coverage";
+
+      cp_cmd : coverpoint cov_cmd {
+         bins add     = {CMD_ADD};
+         bins sub     = {CMD_SUB};
+         bins shl     = {CMD_SHL};
+         bins shr     = {CMD_SHR};
+         bins invalid = {[4'h3:4'h4], 4'h7, [4'h8:4'hF]};
+      }
+      cp_port : coverpoint cov_port {
+         bins port1 = {2'd0};
+         bins port2 = {2'd1};
+         bins port3 = {2'd2};
+         bins port4 = {2'd3};
+      }
+      // the monitor only emits an item once a real response is seen, so only
+      // SUCCESS and ERROR are ever sampled here
+      cp_resp : coverpoint cov_resp {
+         bins success = {RESP_SUCCESS};
+         bins error   = {RESP_ERROR};
+      }
+      // interesting operand corners
+      cp_op1 : coverpoint cov_op1 {
+         bins zero    = {32'h0000_0000};
+         bins one     = {32'h0000_0001};
+         bins max     = {32'hFFFF_FFFF};
+         bins msb     = {32'h8000_0000};
+         bins others  = default;
+      }
+      cp_op2 : coverpoint cov_op2 {
+         bins zero    = {32'h0000_0000};
+         bins one     = {32'h0000_0001};
+         bins max     = {32'hFFFF_FFFF};
+         bins shamt   = {[32'h2:32'h1F]};   // small shift amounts
+         bins others  = default;
+      }
+      // every legal command must be exercised on every port
+      cx_cmd_port : cross cp_cmd, cp_port;
+      // every command must be seen producing both success and error responses
+      cx_cmd_resp : cross cp_cmd, cp_resp;
+   endgroup
+
+   function new(string name = "calc_monitor", uvm_component parent = null);
+      super.new(name,parent);
+      item_collected_port = new("item_collected_port", this);
+      calc_cg = new();
+   endfunction
+
+   function void connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if (!uvm_config_db#(virtual calc_if)::get(this, "", "calc_if", vif))
+        `uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
+   endfunction : connect_phase
+
+   task main_phase(uvm_phase phase);
+      wait_reset_done();
+      // launch one independent collector per port
+      for (int p = 0; p < NUM_PORTS; p++) begin
+         automatic int port = p;
+         fork
+            collect_port(port[1:0]);
+         join_none
+      end
+   endtask : main_phase
+
+   // Collect every request/response pair seen on a single port.
+   task collect_port(bit [1:0] port);
+      calc_seq_item it;
+      int unsigned  wait_cnt;
+      forever begin
+         // wait for the start of a request on this port
+         do @(posedge vif.clk); while (get_cmd(port) === CMD_NOP || vif.rst !== '0);
+
+         it      = calc_seq_item::type_id::create($sformatf("it_p%0d", port));
+         it.port = port;
+         it.cmd  = get_cmd(port);
+         it.op1  = get_data(port);
+
+         // operand2 is presented on the next cycle
+         @(posedge vif.clk);
+         it.op2 = get_data(port);
+
+         // wait for the response on this port (bounded - a non-responding DUT
+         // is reported, not waited on forever); resp stays NONE on timeout so
+         // the scoreboard flags the missing response
+         wait_cnt = 0;
+         do begin
+            @(posedge vif.clk);
+            wait_cnt++;
+         end while (get_resp(port) === RESP_NONE && wait_cnt < RSP_TIMEOUT);
+         it.resp   = get_resp(port);
+         it.result = get_out_data(port);
+
+         num_collected++;
+         `uvm_info(get_type_name(),
+                   $sformatf("Collected: %s", it.convert2string()), UVM_MEDIUM)
+
+         if (coverage_enable) sample_coverage(it);
+         item_collected_port.write(it);
+      end
+   endtask : collect_port
+
+   function void sample_coverage(calc_seq_item it);
+      cov_cmd  = it.cmd;
+      cov_port = it.port;
+      cov_resp = it.resp;
+      cov_op1  = it.op1;
+      cov_op2  = it.op2;
+      calc_cg.sample();
+   endfunction
+
+   //--- per-port signal accessors -------------------------------------------
+   function bit [CMD_WIDTH-1:0] get_cmd(bit [1:0] port);
+      case (port)
+        2'd0 : return vif.req1_cmd_in;
+        2'd1 : return vif.req2_cmd_in;
+        2'd2 : return vif.req3_cmd_in;
+        2'd3 : return vif.req4_cmd_in;
+      endcase
+   endfunction
+
+   function bit [DATA_WIDTH-1:0] get_data(bit [1:0] port);
+      case (port)
+        2'd0 : return vif.req1_data_in;
+        2'd1 : return vif.req2_data_in;
+        2'd2 : return vif.req3_data_in;
+        2'd3 : return vif.req4_data_in;
+      endcase
+   endfunction
+
+   function bit [RESP_WIDTH-1:0] get_resp(bit [1:0] port);
+      case (port)
+        2'd0 : return vif.out_resp1;
+        2'd1 : return vif.out_resp2;
+        2'd2 : return vif.out_resp3;
+        2'd3 : return vif.out_resp4;
+      endcase
+   endfunction
+
+   function bit [DATA_WIDTH-1:0] get_out_data(bit [1:0] port);
+      case (port)
+        2'd0 : return vif.out_data1;
+        2'd1 : return vif.out_data2;
+        2'd2 : return vif.out_data3;
+        2'd3 : return vif.out_data4;
+      endcase
+   endfunction
+
+   task wait_reset_done();
+      while (vif.rst !== '0) @(posedge vif.clk);
+   endtask : wait_reset_done
+
+   function void report_phase(uvm_phase phase);
+      `uvm_info(get_type_name(),
+                $sformatf("Monitor collected %0d transactions, functional coverage = %0.2f%%",
+                          num_collected, calc_cg.get_coverage()), UVM_LOW)
+   endfunction : report_phase
+
+endclass : calc_monitor
+
+`endif

code/vezba10/verif/Agent/calc_seq_item.sv

@@ -0,0 +1,120 @@
+`ifndef CALC_SEQ_ITEM_SV
+ `define CALC_SEQ_ITEM_SV
+
+parameter DATA_WIDTH  = 32;
+parameter RESP_WIDTH  = 2;
+parameter CMD_WIDTH   = 4;
+parameter NUM_PORTS   = 4;
+// Max clock cycles to wait for a response before declaring the request lost.
+// A correct Calc1 answers in a handful of cycles; the timeout only fires on a
+// DUT that never responds, so the environment reports an error instead of
+// hanging forever.
+parameter RSP_TIMEOUT = 64;
+
+//-----------------------------------------------------------------------------
+// Calc1 command encoding (see Vezba 5, Tabela 6).  All other 4-bit values are
+// treated by the design as "invalid" commands.
+//-----------------------------------------------------------------------------
+typedef enum bit [CMD_WIDTH-1:0] {
+   CMD_NOP = 4'b0000, // no operation
+   CMD_ADD = 4'b0001, // result = op1 + op2
+   CMD_SUB = 4'b0010, // result = op1 - op2
+   CMD_SHL = 4'b0101, // result = op1 << op2[4:0]
+   CMD_SHR = 4'b0110  // result = op1 >> op2[4:0]
+} calc_cmd_e;
+
+//-----------------------------------------------------------------------------
+// Calc1 response encoding (see Vezba 5, Tabela 8).
+//-----------------------------------------------------------------------------
+typedef enum bit [RESP_WIDTH-1:0] {
+   RESP_NONE    = 2'b00, // no response this cycle
+   RESP_SUCCESS = 2'b01, // operation successful, data on out_dataX
+   RESP_ERROR   = 2'b10  // overflow / underflow / invalid command
+   // 2'b11 is unused
+} calc_resp_e;
+
+//-----------------------------------------------------------------------------
+// Sequence item / transaction.
+//   - Stimulus (rand)     : port, cmd, op1, op2, delay
+//   - Observed (non-rand) : resp, result   (filled in by the monitor)
+//-----------------------------------------------------------------------------
+class calc_seq_item extends uvm_sequence_item;
+
+   // --- stimulus fields ---------------------------------------------------
+   rand bit [1:0]              port;   // target port 0..3  (-> req1..req4)
+   rand bit [CMD_WIDTH-1:0]    cmd;    // raw 4-bit command (allows invalid)
+   rand bit [DATA_WIDTH-1:0]   op1;    // operand 1
+   rand bit [DATA_WIDTH-1:0]   op2;    // operand 2
+   rand int unsigned           delay;  // idle cycles before issuing the request
+
+   // --- observed fields (driven by the monitor) ---------------------------
+   bit [RESP_WIDTH-1:0]        resp;   // observed out_respX
+   bit [DATA_WIDTH-1:0]        result; // observed out_dataX
+
+   // --- constraints --------------------------------------------------------
+   // A real request always carries a command; NOP would produce no response.
+   constraint c_no_nop  { cmd != CMD_NOP; }
+
+   // By default favour the four legal commands, but keep a small probability
+   // of an illegal command so the random regression exercises that path too.
+   constraint c_cmd_dist {
+      cmd dist {
+         CMD_ADD := 25,
+         CMD_SUB := 25,
+         CMD_SHL := 20,
+         CMD_SHR := 20,
+         [4'h3:4'h4] :/ 5,   // illegal
+         4'h7        :/ 5    // illegal
+      };
+   }
+
+   constraint c_delay { delay inside {[0:6]}; }
+
+   `uvm_object_utils_begin(calc_seq_item)
+      `uvm_field_int (port,   UVM_DEFAULT)
+      `uvm_field_int (cmd,    UVM_DEFAULT)
+      `uvm_field_int (op1,    UVM_DEFAULT)
+      `uvm_field_int (op2,    UVM_DEFAULT)
+      `uvm_field_int (delay,  UVM_DEFAULT | UVM_DEC)
+      `uvm_field_int (resp,   UVM_DEFAULT)
+      `uvm_field_int (result, UVM_DEFAULT)
+   `uvm_object_utils_end
+
+   function new (string name = "calc_seq_item");
+      super.new(name);
+   endfunction
+
+   // True when cmd is one of the four legal Calc1 commands.
+   function bit is_legal_cmd();
+      return (cmd inside {CMD_ADD, CMD_SUB, CMD_SHL, CMD_SHR});
+   endfunction
+
+   // Compact one-line description, handy in logs.
+   function string convert2string();
+      return $sformatf("port=%0d cmd=%s(0x%0h) op1=0x%08h op2=0x%08h -> resp=%s data=0x%08h",
+                       port+1, cmd2string(), cmd, op1, op2, resp2string(), result);
+   endfunction
+
+   function string cmd2string();
+      case (cmd)
+        CMD_NOP : return "NOP";
+        CMD_ADD : return "ADD";
+        CMD_SUB : return "SUB";
+        CMD_SHL : return "SHL";
+        CMD_SHR : return "SHR";
+        default : return "INVALID";
+      endcase
+   endfunction
+
+   function string resp2string();
+      case (resp)
+        RESP_NONE    : return "NONE";
+        RESP_SUCCESS : return "SUCCESS";
+        RESP_ERROR   : return "ERROR";
+        default      : return "RSVD";
+      endcase
+   endfunction
+
+endclass : calc_seq_item
+
+`endif

code/vezba10/verif/Agent/calc_sequencer.sv

@@ -0,0 +1,15 @@
+`ifndef CALC_SEQUENCER_SV
+ `define CALC_SEQUENCER_SV
+
+class calc_sequencer extends uvm_sequencer#(calc_seq_item);
+
+   `uvm_component_utils(calc_sequencer)
+
+   function new(string name = "calc_sequencer", uvm_component parent = null);
+      super.new(name,parent);
+   endfunction
+
+endclass : calc_sequencer
+
+`endif
+