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This commit is contained in:
Nebojša Pilipović
2026-06-12 07:53:32 +02:00
commit 59e71f3297
259 changed files with 29010 additions and 0 deletions
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code/vezba10/xsim.dir/calc_sim/Compile_Options.txt Normal file
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--nolog -L "uvm" -timescale "1ns/10ps" "calc_verif_top" -s "calc_sim"

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code/vezba10/xsim.dir/calc_sim/xsimSettings.ini Normal file
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=0
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
OBJECT_NAME_COLUMN_WIDTH=0
OBJECT_VALUE_COLUMN_WIDTH=0
OBJECT_DATA_TYPE_COLUMN_WIDTH=0
PROCESS_NAME_COLUMN_WIDTH=0
PROCESS_TYPE_COLUMN_WIDTH=0
FRAME_INDEX_COLUMN_WIDTH=0
FRAME_NAME_COLUMN_WIDTH=0
FRAME_FILE_NAME_COLUMN_WIDTH=0
FRAME_LINE_NUM_COLUMN_WIDTH=0
LOCAL_NAME_COLUMN_WIDTH=0
LOCAL_VALUE_COLUMN_WIDTH=0
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1

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code/vezba10/xsim.dir/calc_sim/xsim_script.tcl Normal file
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xsim {calc_sim} -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -autoloadwcfg -runall -sv_seed random

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code/vezba10/xsim.dir/calc_sim/xsimcrash.log Normal file
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code/vezba10/xsim.dir/calc_sim/xsimkernel.log Normal file
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Running: xsim.dir/calc_sim/xsimk -runall -sv_seed random -simmode gui -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -wdb calc_sim.wdb -simrunnum 0 -socket 49855
Design successfully loaded
Design Loading Memory Usage: 44568 KB (Peak: 44568 KB)
Design Loading CPU Usage: 20 ms
Simulation completed
Simulation Memory Usage: 139376 KB (Peak: 183836 KB)
Simulation CPU Usage: 120 ms

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0.7
2020.2
Oct 14 2022
05:07:14
/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_input_stage.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_output_stage.v,,alu_input_stage,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/alu_output_stage.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/calc_top.v,,alu_output_stage,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/calc_top.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/exdbin_mac.v,,calc_top,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/exdbin_mac.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/holdreg.v,,exdbin_mac,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/holdreg.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/mux_out.v,,holdreg,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/mux_out.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/priority.v,,mux_out,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/priority.v,1680513656,verilog,,/home/pilipovic/Downloads/FVH/code/vezba10/dut/shifter.v,,priority1,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/dut/shifter.v,1680513656,verilog,,,,shifter,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent.sv,1680513570,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv,1680513570,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_seq_item.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_sequencer.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_driver.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_monitor.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent.sv,calc_agent_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_driver.sv,1781194218,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_monitor.sv,1781194229,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_seq_item.sv,1781194204,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_sequencer.sv,1680513570,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/calc_config.sv,1781190521,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/configurations_pkg.sv,1680513570,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/Agent/calc_agent_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Configurations/calc_config.sv,configurations_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_base_seq.sv,1781190541,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_lib.sv,1781194763,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_pkg.sv,1781190610,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_base_seq.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_simple_seq.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_seq_lib.sv,calc_seq_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/Sequences/calc_simple_seq.sv,1781190733,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_env.sv,1781190530,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,1680513570,systemVerilog,,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,,calc_if,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_scoreboard.sv,1781190500,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_test_pkg.sv,1781190646,systemVerilog,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_scoreboard.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_env.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_base.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple_2.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_lib.sv;/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_if.sv,calc_test_pkg,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/calc_verif_top.sv,1781190673,systemVerilog,,,/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh,calc_verif_top,,uvm,./verif;./verif/Agent;./verif/Configurations;./verif/Sequences,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_base.sv,1680513570,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_lib.sv,1781194773,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple.sv,1781190742,verilog,,,,,,,,,,,,
/home/pilipovic/Downloads/FVH/code/vezba10/verif/test_simple_2.sv,1781194936,verilog,,,,,,,,,,,,
/tools/Xilinx/Vivado/2022.2/data/xsim/system_verilog/uvm_include/uvm_macros.svh,1665704903,verilog,,,,,,,,,,,,