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code/vezba10/xsim.dir/calc_sim/Compile_Options.txt
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code/vezba10/xsim.dir/calc_sim/Compile_Options.txt
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--nolog -L "uvm" -timescale "1ns/10ps" "calc_verif_top" -s "calc_sim"
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code/vezba10/xsim.dir/calc_sim/xsim.covinfo
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code/vezba10/xsim.dir/calc_sim/xsim.covinfo
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code/vezba10/xsim.dir/calc_sim/xsim.crvsdump
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code/vezba10/xsim.dir/calc_sim/xsim.crvsdump
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code/vezba10/xsim.dir/calc_sim/xsim.dbg
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code/vezba10/xsim.dir/calc_sim/xsim.dbg
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code/vezba10/xsim.dir/calc_sim/xsim.mem
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code/vezba10/xsim.dir/calc_sim/xsim.mem
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code/vezba10/xsim.dir/calc_sim/xsim.reloc
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code/vezba10/xsim.dir/calc_sim/xsim.reloc
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code/vezba10/xsim.dir/calc_sim/xsim.rtti
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code/vezba10/xsim.dir/calc_sim/xsim.rtti
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code/vezba10/xsim.dir/calc_sim/xsim.svtype
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code/vezba10/xsim.dir/calc_sim/xsim.svtype
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code/vezba10/xsim.dir/calc_sim/xsim.type
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code/vezba10/xsim.dir/calc_sim/xsim.type
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code/vezba10/xsim.dir/calc_sim/xsim.xdbg
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code/vezba10/xsim.dir/calc_sim/xsim.xdbg
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code/vezba10/xsim.dir/calc_sim/xsimSettings.ini
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code/vezba10/xsim.dir/calc_sim/xsimSettings.ini
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[General]
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ARRAY_DISPLAY_LIMIT=512
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RADIX=hex
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TIME_UNIT=ns
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TRACE_LIMIT=2147483647
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VHDL_ENTITY_SCOPE_FILTER=true
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VHDL_PACKAGE_SCOPE_FILTER=false
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VHDL_BLOCK_SCOPE_FILTER=true
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VHDL_PROCESS_SCOPE_FILTER=false
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VHDL_PROCEDURE_SCOPE_FILTER=false
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VERILOG_MODULE_SCOPE_FILTER=true
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VERILOG_PACKAGE_SCOPE_FILTER=false
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VERILOG_BLOCK_SCOPE_FILTER=false
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VERILOG_TASK_SCOPE_FILTER=false
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VERILOG_PROCESS_SCOPE_FILTER=false
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INPUT_OBJECT_FILTER=true
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OUTPUT_OBJECT_FILTER=true
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INOUT_OBJECT_FILTER=true
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INTERNAL_OBJECT_FILTER=true
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CONSTANT_OBJECT_FILTER=true
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VARIABLE_OBJECT_FILTER=true
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INPUT_PROTOINST_FILTER=true
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OUTPUT_PROTOINST_FILTER=true
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INOUT_PROTOINST_FILTER=true
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INTERNAL_PROTOINST_FILTER=true
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CONSTANT_PROTOINST_FILTER=true
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VARIABLE_PROTOINST_FILTER=true
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SCOPE_NAME_COLUMN_WIDTH=0
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SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
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SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
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OBJECT_NAME_COLUMN_WIDTH=0
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OBJECT_VALUE_COLUMN_WIDTH=0
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OBJECT_DATA_TYPE_COLUMN_WIDTH=0
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PROCESS_NAME_COLUMN_WIDTH=0
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PROCESS_TYPE_COLUMN_WIDTH=0
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FRAME_INDEX_COLUMN_WIDTH=0
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FRAME_NAME_COLUMN_WIDTH=0
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FRAME_FILE_NAME_COLUMN_WIDTH=0
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FRAME_LINE_NUM_COLUMN_WIDTH=0
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LOCAL_NAME_COLUMN_WIDTH=0
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LOCAL_VALUE_COLUMN_WIDTH=0
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LOCAL_DATA_TYPE_COLUMN_WIDTH=0
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PROTO_NAME_COLUMN_WIDTH=0
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PROTO_VALUE_COLUMN_WIDTH=0
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INPUT_LOCAL_FILTER=1
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OUTPUT_LOCAL_FILTER=1
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INOUT_LOCAL_FILTER=1
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INTERNAL_LOCAL_FILTER=1
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CONSTANT_LOCAL_FILTER=1
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VARIABLE_LOCAL_FILTER=1
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code/vezba10/xsim.dir/calc_sim/xsim_script.tcl
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code/vezba10/xsim.dir/calc_sim/xsim_script.tcl
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xsim {calc_sim} -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -autoloadwcfg -runall -sv_seed random
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code/vezba10/xsim.dir/calc_sim/xsimcrash.log
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code/vezba10/xsim.dir/calc_sim/xsimcrash.log
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code/vezba10/xsim.dir/calc_sim/xsimk
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code/vezba10/xsim.dir/calc_sim/xsimk
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code/vezba10/xsim.dir/calc_sim/xsimkernel.log
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code/vezba10/xsim.dir/calc_sim/xsimkernel.log
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Running: xsim.dir/calc_sim/xsimk -runall -sv_seed random -simmode gui -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -wdb calc_sim.wdb -simrunnum 0 -socket 49855
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Design successfully loaded
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Design Loading Memory Usage: 44568 KB (Peak: 44568 KB)
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Design Loading CPU Usage: 20 ms
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Simulation completed
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Simulation Memory Usage: 139376 KB (Peak: 183836 KB)
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Simulation CPU Usage: 120 ms
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