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Nebojša Pilipović
2026-06-12 07:53:32 +02:00
commit 59e71f3297
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code/vezba10/xsim.dir/calc_sim/xsimkernel.log Normal file
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Running: xsim.dir/calc_sim/xsimk -runall -sv_seed random -simmode gui -testplusarg UVM_TESTNAME=test_random -testplusarg UVM_VERBOSITY=UVM_HIGH -wdb calc_sim.wdb -simrunnum 0 -socket 49855
Design successfully loaded
Design Loading Memory Usage: 44568 KB (Peak: 44568 KB)
Design Loading CPU Usage: 20 ms
Simulation completed
Simulation Memory Usage: 139376 KB (Peak: 183836 KB)
Simulation CPU Usage: 120 ms