This commit is contained in:
2026-06-12 07:53:32 +02:00
commit 59e71f3297
259 changed files with 29010 additions and 0 deletions

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v2_top.sv
v2_driver.sv
v2_memory_if.sv
v2_tr.sv
v2_memory_pkg.sv
v2_memory.sv
-gui
-access +rwc

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`ifndef DRIVER_SV
`define DRIVER_SV
class driver;
newTransaction tr;
virtual memory_if mem_if;
function new(virtual memory_if mem_if);
this.mem_if = mem_if;
endfunction : new
task run();
tr = new();
drive_transaction(tr);
tr.addr = 2'hA;
tr.en = 1'b1;
drive_transaction(tr);
tr.data_i = 8'hAA;
tr.rw = 1'b1;
drive_transaction(tr);
endtask : run
task drive_transaction(newTransaction tr);
$display("Driving transaction:");
tr.display_transaction();
@(posedge mem_if.clk);
mem_if.addr <= tr.addr;
mem_if.data_i <= tr.data_i;
mem_if.en <= tr.en;
mem_if.rw <= tr.rw;
endtask : drive_transaction
endclass : driver
`endif

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`ifndef MEMORY_SV
`define MEMORY_SV
module memory #(
parameter ADDR_WIDTH = 2,
parameter DATA_WIDTH = 8
)
(
input logic clk,
input logic rst,
input logic [ADDR_WIDTH-1 : 0] addr_i,
input logic rw_i,
input logic en_i,
input logic [DATA_WIDTH-1 : 0] data_i,
output logic [DATA_WIDTH-1 : 0] data_o
);
logic [DATA_WIDTH-1 : 0] mem [2**ADDR_WIDTH];
always @(posedge clk or posedge rst) begin
if(rst) begin
for(int i = 0; i < 2**ADDR_WIDTH; i++) begin
mem[i] = 0;
end
end
else begin
if(en_i) begin
if(rw_i) begin
mem[addr_i] <= data_i;
end
else begin
data_o <= mem[addr_i];
end
end
end
end
endmodule : memory
`endif

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`ifndef MEMORY_IF_SV
`define MEMORY_IF_SV
interface memory_if(input clk, input rst);
logic [1 : 0] addr;
logic rw;
logic en;
logic [7 : 0] data_i;
logic [7 : 0] data_o;
endinterface : memory_if
`endif

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`ifndef MEMORY_PKG_SV
`define MEMORY_PKG_SV
package memory_pkg;
`include "v2_tr.sv"
`include "v2_driver.sv"
endpackage : memory_pkg
`endif

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module queue_examples;
int x = 2;
int y = 2;
int q1[$] = {2, 4, 8};
int q2[$] = {2, 4, 8};
initial begin
$display("Inicijalno stanje reda q1: %p", q1);
q1 = {q1, 10};
q1 = {3, q1};
q1 = {q1[0 : x-1], 5, q1[x : $]};
$display("Posle ubacivanja elemenata u q1: %p", q1);
x = q1[0];
$display("x dobija vrednost %0d", x);
q1 = q1[1 : $];
$display("Posle brisanja elemenata iz q1: %p", q1);
x = q1[$];
$display("x dobija vrednost %0d", x);
q1 = q1[0:$-1];
$display("Posle brisanja elemenata iz q1: %p", q1);
q1 = {};
$display("Posle brisanja celog reda q1: %p", q1);
// -------------------------------------------------
$display("Inicijalno stanje reda q2: %p", q2);
q2.push_back(10);
q2.push_front(3);
q2.insert(y, 5);
$display("Posle ubacivanja elemenata u q2: %p", q2);
y = q2.pop_front();
$display("y dobija vrednost %0d", y);
$display("Posle brisanja elemenata iz q2: %p", q2);
y = q2.pop_back();
$display("y dobija vrednost %0d", y);
$display("Posle brisanja elemenata iz q2: %p", q2);
q2.delete();
$display("Posle brisanja celog reda q2: %p", q2);
end
endmodule : queue_examples

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`ifndef TOP_SV
`define TOP_SV
`include "v2_memory.sv"
`include "v2_memory_if.sv"
`include "v2_memory_pkg.sv"
module top;
import memory_pkg::*;
bit clk;
bit rst;
memory_if mem_if(clk, rst);
memory DUT (
.clk (clk),
.rst (rst),
.addr_i (mem_if.addr),
.rw_i (mem_if.rw),
.en_i (mem_if.en),
.data_i (mem_if.data_i),
.data_o (mem_if.data_o)
);
driver drv = new(mem_if);
initial begin
clk = 0;
rst = 1;
#5 rst =0;
#500 $finish();
end
always #5 clk = ~clk;
initial drv.run();
endmodule : top
`endif

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`ifndef TRANSACTION_SV
`define TRANSACTION_SV
class transaction;
bit [1 : 0] addr;
bit [7 : 0] data_i;
function void display_transaction();
$display("\taddr = %0h", this.addr);
$display("\tdata_i = %0h", this.data_i);
endfunction : display_transaction
endclass : transaction
class newTransaction extends transaction;
bit [7 : 0] data_o;
bit rw;
bit en;
function void display_transaction();
super.display_transaction();
$display("\tdata_o = %0h", this.data_o);
$display("\trw = %0h", this.rw);
$display("\ten = %0h", this.en);
endfunction : display_transaction
endclass : newTransaction
`endif