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This commit is contained in:
Nebojša Pilipović
2026-06-12 07:53:32 +02:00
commit 59e71f3297
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code/vezba5-3/vezba5/dut/alu_input_stage.v Normal file
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// Library: calc1
// Module: ALU Input Stage
// Author: Naseer SIddique
module alu_input_stage (alu_data1, alu_data2, hold1_data1, hold1_data2, hold2_data1, hold2_data2, hold3_data1, hold3_data2, hold4_data1, hold4_data2, prio_alu_in_cmd, prio_alu_in_req_id);
output [0:63] alu_data1, alu_data2;
wire [0:63] alu_data1, alu_data2;
input [0:31] hold1_data1, hold1_data2,
hold2_data1, hold2_data2,
hold3_data1, hold3_data2,
hold4_data1, hold4_data2;
input [0:3] prio_alu_in_cmd;
input [0:1] prio_alu_in_req_id;
assign alu_data1[32:63] =
prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data1[0:31] :
prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data1[0:31] :
32'b0;
assign alu_data2[32:63] =
prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data2[0:31] :
prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data2[0:31] :
32'b0;
assign alu_data1[0:31] = 32'b0;
assign alu_data2[0:31] = 32'b0;
endmodule // alu_input_stage

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code/vezba5-3/vezba5/dut/alu_output_stage.v Normal file
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// Library: calc1
// Module: ALU Output Stage
// Author: Naseer Siddique
module alu_output_stage(out_data1, out_data2, out_data3, out_data4, out_resp1, out_resp2, out_resp3, out_resp4, c_clk,alu_overflow, alu_result, local_error_found, prio_alu_out_req_id, prio_alu_out_vld, reset);
output [0:31] out_data1, out_data2, out_data3, out_data4;
output [0:1] out_resp1, out_resp2, out_resp3, out_resp4;
input [0:63] alu_result;
input [0:1] prio_alu_out_req_id;
input [1:7] reset;
input c_clk,
alu_overflow,
local_error_found,
prio_alu_out_vld;
wire [0:31] hold_data;
wire [0:1] hold_resp, hold_id;
assign hold_id[0:1] = prio_alu_out_req_id[0:1];
assign hold_resp[0:1] =
(~prio_alu_out_vld) ? 2'b00 :
(~local_error_found) ? 2'b01 :
(alu_result[31]) ? 2'b10 :
2'b01;
assign hold_data[0:31] = (prio_alu_out_vld) ? alu_result[32:63] : 32'b0;
assign out_resp1[0:1] = (hold_id[0:1] == 2'b00) ? hold_resp[0:1] : 2'b00;
assign out_resp2[0:1] = (hold_id[0:1] == 2'b01) ? hold_resp[0:1] : 2'b00;
assign out_resp3[0:1] = (hold_id[0:1] == 2'b10) ? hold_resp[0:1] : 2'b00;
assign out_resp4[0:1] = (hold_id[0:1] == 2'b11) ? hold_resp[0:1] : 2'b00;
assign out_data1[0:31] = (hold_id[0:1] == 2'b00) ? hold_data[0:31] : 32'b0;
assign out_data2[0:31] = (hold_id[0:1] == 2'b01) ? hold_data[0:31] : 32'b0;
assign out_data3[0:31] = (hold_id[0:1] == 2'b10) ? hold_data[0:31] : 32'b0;
assign out_data4[0:31] = (hold_id[0:1] == 2'b11) ? hold_data[0:31] : 32'b0;
endmodule

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code/vezba5-3/vezba5/dut/calc_top.v Normal file
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// Library: calc1
// Module: Top-level wiring
// Author: Naseer Siddique
//`include "alu_input_stage.v"
//`include "alu_output_stage.v"
//`include "exdbin_mac.v"
//`include "holdreg.v"
//`include "mux_out.v"
//`include "shifter.v"
//`include "priority.v"
module calc_top (out_data1, out_data2, out_data3, out_data4, out_resp1, out_resp2, out_resp3, out_resp4, c_clk, req1_cmd_in, req1_data_in, req2_cmd_in, req2_data_in, req3_cmd_in, req3_data_in, req4_cmd_in, req4_data_in, reset);
output [0:31] out_data1,
out_data2,
out_data3,
out_data4;
output [0:1] out_resp1,
out_resp2,
out_resp3,
out_resp4;
input c_clk;
input [0:3] req1_cmd_in,
req2_cmd_in,
req3_cmd_in,
req4_cmd_in;
input [0:31] req1_data_in,
req2_data_in,
req3_data_in,
req4_data_in;
input [1:7] reset;
wire [0:63] add_sum,
fxu_areg_q,
fxu_breg_q,
shift_out,
shift_places,
shift_val;
wire [0:31] hold1_data1,
hold1_data2,
hold2_data1,
hold2_data2,
hold3_data1,
hold3_data2,
hold4_data1,
hold4_data2,
mux1_req_data1,
mux1_req_data2,
mux2_req_data1,
mux2_req_data2,
mux3_req_data1,
mux3_req_data2,
mux4_req_data1,
mux4_req_data2;
wire [0:3] hold1_prio_req,
hold2_prio_req,
hold3_prio_req,
hold4_prio_req,
prio_alu1_in_cmd,
prio_alu2_in_cmd;
wire [0:1] mux1_req_resp1,
mux1_req_resp2,
mux2_req_resp1,
mux2_req_resp2,
mux3_req_resp1,
mux3_req_resp2,
mux4_req_resp1,
mux4_req_resp2,
prio_alu1_in_req_id,
prio_alu1_out_req_id,
prio_alu2_in_req_id,
prio_alu2_out_req_id;
wire prio_alu1_out_vld,
prio_alu2_out_vld,
add_ovfl,
shift_ovfl;
wire [0:3] error_found;
assign error_found = 4'b0000;
exdbin_mac adder (
.alu_cmd ( prio_alu1_in_cmd[0:3] ),
.bin_ovfl ( add_ovfl ),
.bin_sum ( add_sum[0:63] ),
.fxu_areg_q ( fxu_areg_q[0:63] ),
.fxu_breg_q ( fxu_breg_q[0:63] ),
.local_error_found ( error_found[0] )
);
holdreg holdreg1(
.c_clk ( c_clk ),
.hold_data1 ( hold1_data1[0:31] ),
.hold_data2 ( hold1_data2[0:31] ),
.hold_prio_req ( hold1_prio_req[0:3] ),
.req_cmd_in ( req1_cmd_in[0:3] ),
.req_data_in ( req1_data_in[0:31] ),
.reset ( reset [1: 7] )
);
holdreg holdreg2(
.c_clk ( c_clk ),
.hold_data1 ( hold2_data1[0:31] ),
.hold_data2 ( hold2_data2[0:31] ),
.hold_prio_req ( hold2_prio_req[0:3] ),
.req_cmd_in ( req2_cmd_in[0:3] ),
.req_data_in ( req2_data_in[0:31] ),
.reset ( reset [1: 7] )
);
holdreg holdreg3(
.c_clk ( c_clk ),
.hold_data1 ( hold3_data1[0:31] ),
.hold_data2 ( hold3_data2[0:31] ),
.hold_prio_req ( hold3_prio_req[0:3] ),
.req_cmd_in ( req3_cmd_in[0:3] ),
.req_data_in ( req3_data_in[0:31] ),
.reset ( reset [1: 7] )
);
holdreg holdreg4(
.c_clk ( c_clk ),
.hold_data1 ( hold4_data1[0:31] ),
.hold_data2 ( hold4_data2[0:31] ),
.hold_prio_req ( hold4_prio_req[0:3] ),
.req_cmd_in ( req4_cmd_in[0:3] ),
.req_data_in ( req4_data_in[0:31] ),
.reset ( reset [1: 7] )
);
alu_input_stage in_stage1(
.alu_data1 ( fxu_areg_q[0:63]),
.alu_data2 ( fxu_breg_q[0:63]),
.hold1_data1 ( hold1_data1[0:31]),
.hold1_data2 ( hold1_data2[0:31]),
.hold2_data1 ( hold2_data1[0:31]),
.hold2_data2 ( hold2_data2[0:31]),
.hold3_data1 ( hold3_data1[0:31]),
.hold3_data2 ( hold3_data2[0:31]),
.hold4_data1 ( hold4_data1[0:31]),
.hold4_data2 ( hold4_data2[0:31]),
.prio_alu_in_cmd ( prio_alu1_in_cmd[0:3]),
.prio_alu_in_req_id ( prio_alu1_in_req_id[0:1])
);
alu_input_stage in_stage2(
.alu_data1 ( shift_val[0:63]),
.alu_data2 ( shift_places[0:63]),
.hold1_data1 ( hold1_data1[0:31]),
.hold1_data2 ( hold1_data2[0:31]),
.hold2_data1 ( hold2_data1[0:31]),
.hold2_data2 ( hold2_data2[0:31]),
.hold3_data1 ( hold3_data1[0:31]),
.hold3_data2 ( hold3_data2[0:31]),
.hold4_data1 ( hold4_data1[0:31]),
.hold4_data2 ( hold4_data2[0:31]),
.prio_alu_in_cmd ( prio_alu2_in_cmd[0:3]),
.prio_alu_in_req_id ( prio_alu2_in_req_id[0:1])
);
mux_out mux_out1(
.req_data1 ( mux1_req_data1[0:31]),
.req_data2 ( mux1_req_data2[0:31]),
.req_data ( out_data1[0:31]),
.req_resp1 ( mux1_req_resp1[0:1]),
.req_resp2 ( mux1_req_resp2[0:1]),
.req_resp ( out_resp1[0:1])
);
mux_out mux_out2(
.req_data1 ( mux2_req_data1[0:31]),
.req_data2 ( mux2_req_data2[0:31]),
.req_data ( out_data2[0:31]),
.req_resp1 ( mux2_req_resp1[0:1]),
.req_resp2 ( mux2_req_resp2[0:1]),
.req_resp ( out_resp2[0:1])
);
mux_out mux_out3(
.req_data1 ( mux3_req_data1[0:31]),
.req_data2 ( mux3_req_data2[0:31]),
.req_data ( out_data3[0:31]),
.req_resp1 ( mux3_req_resp1[0:1]),
.req_resp2 ( mux3_req_resp2[0:1]),
.req_resp ( out_resp3[0:1])
);
mux_out mux_out4(
.req_data1 ( mux4_req_data1[0:31]),
.req_data2 ( mux4_req_data2[0:31]),
.req_data ( out_data4[0:31]),
.req_resp1 ( mux4_req_resp1[0:1]),
.req_resp2 ( mux4_req_resp2[0:1]),
.req_resp ( out_resp4[0:1])
);
alu_output_stage out_stage1(
.alu_overflow ( add_ovfl),
.alu_result ( add_sum[0:63]),
.c_clk ( c_clk),
.local_error_found ( error_found[2]),
.out_data1 ( mux1_req_data1[0:31]),
.out_data2 ( mux2_req_data1[0:31]),
.out_data3 ( mux3_req_data1[0:31]),
.out_data4 ( mux4_req_data1[0:31]),
.out_resp1 ( mux1_req_resp1[0:1]),
.out_resp2 ( mux2_req_resp1[0:1]),
.out_resp3 ( mux3_req_resp1[0:1]),
.out_resp4 ( mux4_req_resp1[0:1]),
.prio_alu_out_req_id ( prio_alu1_out_req_id[0:1]),
.prio_alu_out_vld ( prio_alu1_out_vld ),
.reset ( reset[1:7])
);
alu_output_stage out_stage2(
.alu_overflow ( shift_ovfl),
.alu_result ( shift_out[0:63]),
.c_clk ( c_clk),
.local_error_found ( error_found[2]),
.out_data1 ( mux1_req_data2[0:31]),
.out_data2 ( mux2_req_data2[0:31]),
.out_data3 ( mux3_req_data2[0:31]),
.out_data4 ( mux4_req_data2[0:31]),
.out_resp1 ( mux1_req_resp2[0:1]),
.out_resp2 ( mux2_req_resp2[0:1]),
.out_resp3 ( mux3_req_resp2[0:1]),
.out_resp4 ( mux4_req_resp2[0:1]),
.prio_alu_out_req_id ( prio_alu2_out_req_id[0:1]),
.prio_alu_out_vld ( prio_alu2_out_vld ),
.reset ( reset[1:7])
);
priority1 priority_logic (
.c_clk ( c_clk),
.hold1_prio_req ( hold1_prio_req[0:3]),
.hold2_prio_req ( hold2_prio_req[0:3]),
.hold3_prio_req ( hold3_prio_req[0:3]),
.hold4_prio_req ( hold4_prio_req[0:3]),
.local_error_found ( error_found[3]),
.prio_alu1_in_cmd ( prio_alu1_in_cmd[0:3]),
.prio_alu1_in_req_id ( prio_alu1_in_req_id[0:1]),
.prio_alu1_out_req_id ( prio_alu1_out_req_id[0:1]),
.prio_alu1_out_vld ( prio_alu1_out_vld),
.prio_alu2_in_cmd ( prio_alu2_in_cmd[0:3]),
.prio_alu2_in_req_id ( prio_alu2_in_req_id[0:1]),
.prio_alu2_out_req_id ( prio_alu2_out_req_id[0:1]),
.prio_alu2_out_vld ( prio_alu2_out_vld),
.reset ( reset[1:7])
);
shifter shifter1(
.bin_ovfl ( shift_ovfl),
.local_error_found ( error_found[1]),
.shift_cmd ( prio_alu2_in_cmd[0:3]),
.shift_out ( shift_out[0:63]),
.shift_places ( shift_places[0:63]),
.shift_val ( shift_val[0:63])
);
endmodule // calc1_top

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code/vezba5-3/vezba5/dut/exdbin_mac.v Normal file
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code/vezba5-3/vezba5/dut/holdreg.v Normal file
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// Library: calc1
// Module: Hold Register
// Author: Naseer Siddique
module holdreg(hold_data1, hold_data2, hold_prio_req, c_clk, req_cmd_in, req_data_in, reset);
input c_clk;
input [0:3] req_cmd_in;
input [1:7] reset;
input [0:31] req_data_in;
output [0:3] hold_prio_req;
output [0:31] hold_data1, hold_data2;
reg [0:3] cmd_hold, hold_prio_reg;
wire [0:3] cmd_hold_q;
reg [0:31] hold_data1_q, hold_data2_q;
always
@ (posedge c_clk) begin
fork
cmd_hold[0:3] <= (reset[1] == 1) ? 4'b0 : req_cmd_in[0:3];
hold_prio_reg[0:3] <= cmd_hold[0:3];
join
end
always
@ (posedge c_clk) begin
fork
hold_data1_q[0:31] <=
(reset[1]) ? 32'b0 :
(req_cmd_in[0:3] != 4'b0) ? req_data_in[0:31] :
hold_data1_q[0:31];
hold_data2_q[0:31] <=
(reset[1]) ? 32'b0 : (cmd_hold[0:3] != 4'b0) ?
req_data_in[0:31] : hold_data2_q[0:31];
join
end
assign hold_data1 = hold_data1_q;
assign hold_data2 = hold_data2_q;
assign hold_prio_req = hold_prio_reg;
endmodule // holdreg

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code/vezba5-3/vezba5/dut/mux_out.v Normal file
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// Library: calc1
// Module: Output Mux
// Author: Naseer Siddique
module mux_out(req_data, req_resp, req_data1, req_data2, req_resp1, req_resp2);
output [0:31] req_data;
output [0:1] req_resp;
input [0:31] req_data1, req_data2;
input [0:1] req_resp1, req_resp2;
assign req_resp[0:1] =
(req_resp1[0:1] != 2'b00) ? req_resp1 :
( req_resp2[0:1] != 2'b00 ) ? req_resp2 :
2'b00;
assign req_data[0:31] =
( req_resp1[0:1] != 2'b00 ) ? req_data1 :
( req_resp2[0:1] != 2'b00 ) ? req_data2 :
32'b0;
endmodule // mux_out

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// Library: calc1
// Priority Logic
// Author: Naseer Siddique
module priority1 ( prio_alu1_in_cmd, prio_alu1_in_req_id, prio_alu1_out_req_id, prio_alu1_out_vld, prio_alu2_in_cmd, prio_alu2_in_req_id, prio_alu2_out_req_id, prio_alu2_out_vld, c_clk, hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req, local_error_found, reset);
output [0:3] prio_alu1_in_cmd, prio_alu2_in_cmd;
output [0:1] prio_alu1_out_req_id, prio_alu1_in_req_id, prio_alu2_in_req_id, prio_alu2_out_req_id;
output prio_alu1_out_vld, prio_alu2_out_vld;
input c_clk, local_error_found;
input [0:3] hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req;
input [1:7] reset;
reg [0:3] cmd1, cmd2, cmd3, cmd4;
reg delay1, delay2;
wire cmd1_reset, cmd2_reset, cmd3_reset, cmd4_reset;
reg [0:1] prio_req1_id_q, prio_req2_id_q;
reg prio_alu1_out_vld_q, prio_alu2_out_vld_q;
always
@ (posedge c_clk) begin
if (reset[1]) begin
cmd1 <= 0;
cmd2 <= 0;
cmd3 <= 0;
cmd4 <= 0;
end
else begin
fork
delay1 <= prio_alu1_out_vld_q;
delay2 <= prio_alu2_out_vld_q;
cmd1[0:3] <=
(hold1_prio_req[0:3] != 4'b0) ? hold1_prio_req[0:3] :
(cmd1_reset) ? 4'b0 :
cmd1[0:3];
cmd2[0:3] <=
(hold2_prio_req[0:3] != 4'b0) ? hold2_prio_req[0:3] :
(cmd2_reset) ? 4'b0 :
cmd2[0:3];
cmd3[0:3] <=
(hold3_prio_req[0:3] != 4'b0) ? hold3_prio_req[0:3] :
(cmd3_reset) ? 4'b0 :
cmd3[0:3];
cmd4[0:3] <=
(hold4_prio_req[0:3] != 4'b0) ? hold4_prio_req[0:3] :
(cmd4_reset) ? 4'b0 :
cmd4[0:3];
join
end
end // always @ (posedge c_clk)
always
@ (delay1 or delay2 or cmd1 or cmd2 or cmd3 or cmd4) begin
if (delay1)
prio_alu1_out_vld_q <= 1'b0;
else if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
prio_alu1_out_vld_q <= 1'b1;
else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
prio_alu1_out_vld_q <= 1'b1;
else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
prio_alu1_out_vld_q <= 1'b1;
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) && local_error_found )
prio_alu1_out_vld_q <= 1'b1;
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
prio_alu1_out_vld_q <= 1'b0;
else prio_alu1_out_vld_q <= 1'b0;
if (delay2)
prio_alu2_out_vld_q <= 1'b0;
else if (cmd1 > 4'b0011)
prio_alu2_out_vld_q <= 1'b1;
else if (cmd2 > 4'b0011)
prio_alu2_out_vld_q <= 1'b1;
else if (cmd3 > 4'b0011)
prio_alu2_out_vld_q <= 1'b1;
else if (cmd4 > 4'b0011)
prio_alu2_out_vld_q <= 1'b1;
else prio_alu2_out_vld_q <= 1'b0;
if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
prio_req1_id_q[0:1] <= 2'b00;
else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
prio_req1_id_q[0:1] <= 2'b01;
else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
prio_req1_id_q[0:1] <= 2'b10;
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
prio_req1_id_q[0:1] <= 2'b11;
else prio_req1_id_q[0:1] <= 2'b00;
if ( cmd1 > 4'b0011 )
prio_req2_id_q <= 2'b00;
else if ( cmd2 > 4'b0011 )
prio_req2_id_q <= 2'b01;
else if ( cmd3 > 4'b0011 )
prio_req2_id_q <= 2'b10;
else if ( cmd4 > 4'b0011 )
prio_req2_id_q <= 2'b11;
else prio_req2_id_q <= 2'b00;
end // always @ (delay1 or or delay2 or cmd1 or cmd2 or cmd3 or cmd4)
assign prio_alu1_in_req_id[0:1] = prio_req1_id_q[0:1];
assign prio_alu2_in_req_id[0:1] = prio_req2_id_q[0:1];
assign prio_alu1_out_req_id[0:1] = prio_req1_id_q[0:1];
assign prio_alu2_out_req_id[0:1] = prio_req2_id_q[0:1];
assign prio_alu1_out_vld = prio_alu1_out_vld_q;
assign prio_alu2_out_vld = prio_alu2_out_vld_q;
assign prio_alu1_in_cmd[0:3] =
(prio_req1_id_q[0:1] == 2'b00) ? cmd1[0:3] :
(prio_req1_id_q[0:1] == 2'b01) ? cmd2[0:3] :
(prio_req1_id_q[0:1] == 2'b10) ? cmd3[0:3] :
(prio_req1_id_q[0:1] == 2'b11) ? cmd4[0:3] :
4'b0;
assign prio_alu2_in_cmd[0:3] =
(prio_req2_id_q[0:1] == 2'b00) ? cmd1[0:3] :
(prio_req2_id_q[0:1] == 2'b01) ? cmd2[0:3] :
(prio_req2_id_q[0:1] == 2'b10) ? cmd3[0:3] :
(prio_req2_id_q[0:1] == 2'b11) ? cmd4[0:3] :
4'b0;
assign cmd1_reset =
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b00) ) ? 1 :
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b00) ) ? 1 :
0;
assign cmd2_reset =
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b01) ) ? 1 :
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b01) ) ? 1 :
0;
assign cmd3_reset =
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b10) ) ? 1 :
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b10) ) ? 1 :
0;
assign cmd4_reset =
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b11) ) ? 1 :
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b11) ) ? 1 :
0;
endmodule // priority

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code/vezba5-3/vezba5/dut/shifter.v Normal file
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28
code/vezba5-3/vezba5/v5_run.f Normal file
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-sv +incdir+./verif
-sv +incdir+./verif/Agent
./dut/alu_input_stage.v
./dut/alu_output_stage.v
./dut/exdbin_mac.v
./dut/holdreg.v
./dut/mux_out.v
./dut/shifter.v
./dut/priority.v
./dut/calc_top.v
-sv ./verif/Agent/v5_calc_agent_pkg.sv
-sv ./verif/Agent/v5_calc_seq_item.sv
-sv ./verif/calc_if.sv
-sv ./verif/v5_calc_test_pkg.sv
-sv ./verif/v5_calc_test_simple.sv
-sv ./verif/v5_calc_verif_top.sv
-uvmhome "/eda/cadence/2019-20/RHELx86/XCELIUM_19.03.013/tools/methodology/UVM/CDNS-1.2/"
-uvm +UVM_TESTNAME=test_simple
#-LINEDEBUG
-access +rwc
-disable_sem2009
-nowarn "MEMODR"
-timescale 1ns/10ps

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`ifndef CALC_IF_SV
`define CALC_IF_SV
interface calc_if (input clk, logic [6 : 0] rst);
parameter DATA_WIDTH = 32;
parameter RESP_WIDTH = 2;
parameter CMD_WIDTH = 4;
logic [DATA_WIDTH - 1 : 0] out_data1;
logic [DATA_WIDTH - 1 : 0] out_data2;
logic [DATA_WIDTH - 1 : 0] out_data3;
logic [DATA_WIDTH - 1 : 0] out_data4;
logic [RESP_WIDTH - 1 : 0] out_resp1;
logic [RESP_WIDTH - 1 : 0] out_resp2;
logic [RESP_WIDTH - 1 : 0] out_resp3;
logic [RESP_WIDTH - 1 : 0] out_resp4;
logic [CMD_WIDTH - 1 : 0] req1_cmd_in;
logic [DATA_WIDTH - 1 : 0] req1_data_in;
logic [CMD_WIDTH - 1 : 0] req2_cmd_in;
logic [DATA_WIDTH - 1 : 0] req2_data_in;
logic [CMD_WIDTH - 1 : 0] req3_cmd_in;
logic [DATA_WIDTH - 1 : 0] req3_data_in;
logic [CMD_WIDTH - 1 : 0] req4_cmd_in;
logic [DATA_WIDTH - 1 : 0] req4_data_in;
endinterface : calc_if
`endif

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`ifndef V5_CALC_TEST_PKG_SV
`define V5_CALC_TEST_PKG_SV
package calc_test_pkg;
// import the UVM library
`include "uvm_macros.svh" // Include the UVM macros
import uvm_pkg::*;
// import test class
`include "calc_test_simple.sv"
endpackage
`include "calc_if.sv"
`endif;

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`ifndef TEST_SIMPLE_SV
`define TEST_SIMPLE_SV
class test_simple extends uvm_test;
`uvm_component_utils(test_simple)
virtual interface calc_if vif;
function new(string name = "test_simple", uvm_component parent = null);
super.new(name,parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_type_name(), "Starting build phase...", UVM_LOW)
// Preuzimanje virtuelnog interfejsa iz konfiguracione baze podataka.
if (!uvm_config_db#(virtual calc_if)::get(null, "*", "calc_if", vif))
`uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
// ...
endfunction : build_phase
task main_phase(uvm_phase phase);
super.main_phase(phase);
phase.raise_objection(this); //objasnjenje u materijalu za vezbu 6
`uvm_info(get_type_name(), "Starting main phase...", UVM_LOW)
//postavljanje komande
vif.req1_cmd_in = 4'b0001;
//postavljanje prvog podatka
vif.req1_data_in = 32'h0001;
//Cekanje 1 takt
@(posedge vif.clk);
//Uklanjanje komande
vif.req1_cmd_in = 4'b0000;
//Postavljanje drugog podatka
vif.req1_data_in = 32'h0002;
// ...
#1000ns;
phase.drop_objection(this); //objasnjenje u materijalu za vezbu 6
endtask : main_phase
endclass : test_simple
`endif

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code/vezba5-3/vezba5/verif/calc_verif_top.sv Normal file
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module calc_verif_top;
import uvm_pkg::*; // import the UVM library
`include "uvm_macros.svh" // Include the UVM macros
import calc_test_pkg::*;
logic clk;
logic [6 : 0] rst;
// interface
calc_if calc_vif(clk, rst);
// DUT
calc_top DUT(
.c_clk ( clk ),
.reset ( rst ),
.out_data1 ( calc_vif.out_data1 ),
.out_data2 ( calc_vif.out_data2 ),
.out_data3 ( calc_vif.out_data3 ),
.out_data4 ( calc_vif.out_data4 ),
.out_resp1 ( calc_vif.out_resp1 ),
.out_resp2 ( calc_vif.out_resp2 ),
.out_resp3 ( calc_vif.out_resp3 ),
.out_resp4 ( calc_vif.out_resp4 ),
.req1_cmd_in ( calc_vif.req1_cmd_in ),
.req1_data_in ( calc_vif.req1_data_in ),
.req2_cmd_in ( calc_vif.req2_cmd_in ),
.req2_data_in ( calc_vif.req2_data_in ),
.req3_cmd_in ( calc_vif.req3_cmd_in ),
.req3_data_in ( calc_vif.req3_data_in ),
.req4_cmd_in ( calc_vif.req4_cmd_in ),
.req4_data_in ( calc_vif.req4_data_in )
);
// run test
initial begin
// Ubacivanje interfejsa u konfiguracionu bazu podataka
uvm_config_db#(virtual calc_if)::set(null, "*", "calc_if", calc_vif);
run_test("test_simple");
end
// clock and reset init.
initial begin
clk <= 0;
rst <= 1;
#50 rst <= 0;
end
// clock generation
always #50 clk = ~clk;
endmodule : calc_verif_top