init

code/vezba5-3/vezba5/verif/calc_if.sv

@@ -0,0 +1,29 @@
+`ifndef CALC_IF_SV
+ `define CALC_IF_SV
+
+interface calc_if (input clk, logic [6 : 0] rst);
+
+   parameter DATA_WIDTH = 32;
+   parameter RESP_WIDTH = 2;
+   parameter CMD_WIDTH = 4;
+
+   logic [DATA_WIDTH - 1 : 0]  out_data1;
+   logic [DATA_WIDTH - 1 : 0]  out_data2;
+   logic [DATA_WIDTH - 1 : 0]  out_data3;
+   logic [DATA_WIDTH - 1 : 0]  out_data4;
+   logic [RESP_WIDTH - 1 : 0]  out_resp1;
+   logic [RESP_WIDTH - 1 : 0]  out_resp2;
+   logic [RESP_WIDTH - 1 : 0]  out_resp3;
+   logic [RESP_WIDTH - 1 : 0]  out_resp4;
+   logic [CMD_WIDTH - 1 : 0]   req1_cmd_in;
+   logic [DATA_WIDTH - 1 : 0]  req1_data_in;
+   logic [CMD_WIDTH - 1 : 0]   req2_cmd_in;
+   logic [DATA_WIDTH - 1 : 0]  req2_data_in;
+   logic [CMD_WIDTH - 1 : 0]   req3_cmd_in;
+   logic [DATA_WIDTH - 1 : 0]  req3_data_in;
+   logic [CMD_WIDTH - 1 : 0]   req4_cmd_in;
+   logic [DATA_WIDTH - 1 : 0]  req4_data_in;
+
+endinterface : calc_if
+
+`endif

code/vezba5-3/vezba5/verif/calc_test_pkg.sv

@@ -0,0 +1,11 @@
+`ifndef V5_CALC_TEST_PKG_SV
+ `define V5_CALC_TEST_PKG_SV
+package calc_test_pkg;
+// import the UVM library
+`include "uvm_macros.svh" // Include the UVM macros
+import uvm_pkg::*;
+// import test class
+`include "calc_test_simple.sv"
+endpackage
+`include "calc_if.sv"
+`endif;

code/vezba5-3/vezba5/verif/calc_test_simple.sv

@@ -0,0 +1,49 @@
+`ifndef TEST_SIMPLE_SV
+ `define TEST_SIMPLE_SV
+
+class test_simple extends uvm_test;
+
+   `uvm_component_utils(test_simple)
+
+   virtual interface calc_if vif;
+
+   function new(string name = "test_simple", uvm_component parent = null);
+      super.new(name,parent);
+   endfunction : new
+
+   function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      
+      `uvm_info(get_type_name(), "Starting build phase...", UVM_LOW)
+
+      // Preuzimanje virtuelnog interfejsa iz konfiguracione baze podataka.
+      if (!uvm_config_db#(virtual calc_if)::get(null, "*", "calc_if", vif))
+        `uvm_fatal("NOVIF",{"virtual interface must be set:",get_full_name(),".vif"})
+      // ...
+   endfunction : build_phase
+
+   
+   task main_phase(uvm_phase phase);
+      super.main_phase(phase);
+      phase.raise_objection(this); //objasnjenje u materijalu za vezbu 6
+      
+      
+      `uvm_info(get_type_name(), "Starting main phase...", UVM_LOW)
+      //postavljanje komande
+      vif.req1_cmd_in = 4'b0001;
+      //postavljanje prvog podatka
+      vif.req1_data_in = 32'h0001;
+      //Cekanje 1 takt
+      @(posedge vif.clk);
+      //Uklanjanje komande      
+      vif.req1_cmd_in = 4'b0000;
+      //Postavljanje drugog podatka
+      vif.req1_data_in = 32'h0002;
+      // ...
+      #1000ns;
+      phase.drop_objection(this); //objasnjenje u materijalu za vezbu 6
+   endtask : main_phase
+
+endclass : test_simple
+
+`endif

code/vezba5-3/vezba5/verif/calc_verif_top.sv

@@ -0,0 +1,53 @@
+module calc_verif_top;
+
+   import uvm_pkg::*;     // import the UVM library
+   `include "uvm_macros.svh" // Include the UVM macros
+
+   import calc_test_pkg::*;   
+
+   logic clk;
+   logic [6 : 0] rst;
+
+   // interface
+   calc_if calc_vif(clk, rst);
+
+   // DUT
+   calc_top DUT(
+                .c_clk        ( clk ),
+                .reset        ( rst ),
+                .out_data1    ( calc_vif.out_data1 ),
+                .out_data2    ( calc_vif.out_data2 ),
+                .out_data3    ( calc_vif.out_data3 ),
+                .out_data4    ( calc_vif.out_data4 ),
+                .out_resp1    ( calc_vif.out_resp1 ),
+                .out_resp2    ( calc_vif.out_resp2 ),
+                .out_resp3    ( calc_vif.out_resp3 ),
+                .out_resp4    ( calc_vif.out_resp4 ),
+                .req1_cmd_in  ( calc_vif.req1_cmd_in ),
+                .req1_data_in ( calc_vif.req1_data_in ),
+                .req2_cmd_in  ( calc_vif.req2_cmd_in ),
+                .req2_data_in ( calc_vif.req2_data_in ),
+                .req3_cmd_in  ( calc_vif.req3_cmd_in ),
+                .req3_data_in ( calc_vif.req3_data_in ),
+                .req4_cmd_in  ( calc_vif.req4_cmd_in ),
+                .req4_data_in ( calc_vif.req4_data_in )
+                );
+
+   // run test
+   initial begin
+      // Ubacivanje interfejsa u konfiguracionu bazu podataka      
+      uvm_config_db#(virtual calc_if)::set(null, "*", "calc_if", calc_vif);
+      run_test("test_simple");
+   end
+
+   // clock and reset init.
+   initial begin
+      clk <= 0;
+      rst <= 1;
+      #50 rst <= 0;
+   end
+
+   // clock generation
+   always #50 clk = ~clk;
+
+endmodule : calc_verif_top