init
This commit is contained in:
36
code/vezba6_7/dut/alu_input_stage.v
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36
code/vezba6_7/dut/alu_input_stage.v
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// Library: calc1
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// Module: ALU Input Stage
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// Author: Naseer SIddique
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module alu_input_stage (alu_data1, alu_data2, hold1_data1, hold1_data2, hold2_data1, hold2_data2, hold3_data1, hold3_data2, hold4_data1, hold4_data2, prio_alu_in_cmd, prio_alu_in_req_id);
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output [0:63] alu_data1, alu_data2;
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wire [0:63] alu_data1, alu_data2;
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input [0:31] hold1_data1, hold1_data2,
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hold2_data1, hold2_data2,
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hold3_data1, hold3_data2,
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hold4_data1, hold4_data2;
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input [0:3] prio_alu_in_cmd;
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input [0:1] prio_alu_in_req_id;
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assign alu_data1[32:63] =
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prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data1[0:31] :
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prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data1[0:31] :
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prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data1[0:31] :
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prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data1[0:31] :
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32'b0;
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assign alu_data2[32:63] =
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prio_alu_in_req_id[0:1] == 2'b00 ? hold1_data2[0:31] :
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prio_alu_in_req_id[0:1] == 2'b01 ? hold2_data2[0:31] :
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prio_alu_in_req_id[0:1] == 2'b10 ? hold3_data2[0:31] :
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prio_alu_in_req_id[0:1] == 2'b11 ? hold4_data2[0:31] :
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32'b0;
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assign alu_data1[0:31] = 32'b0;
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assign alu_data2[0:31] = 32'b0;
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endmodule // alu_input_stage
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47
code/vezba6_7/dut/alu_output_stage.v
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47
code/vezba6_7/dut/alu_output_stage.v
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@@ -0,0 +1,47 @@
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// Library: calc1
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// Module: ALU Output Stage
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// Author: Naseer Siddique
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module alu_output_stage(out_data1, out_data2, out_data3, out_data4, out_resp1, out_resp2, out_resp3, out_resp4, c_clk,alu_overflow, alu_result, local_error_found, prio_alu_out_req_id, prio_alu_out_vld, reset);
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output [0:31] out_data1, out_data2, out_data3, out_data4;
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output [0:1] out_resp1, out_resp2, out_resp3, out_resp4;
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input [0:63] alu_result;
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input [0:1] prio_alu_out_req_id;
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input [1:7] reset;
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input c_clk,
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alu_overflow,
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local_error_found,
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prio_alu_out_vld;
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wire [0:31] hold_data;
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wire [0:1] hold_resp, hold_id;
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assign hold_id[0:1] = prio_alu_out_req_id[0:1];
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assign hold_resp[0:1] =
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(~prio_alu_out_vld) ? 2'b00 :
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(~local_error_found) ? 2'b01 :
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(alu_result[31]) ? 2'b10 :
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2'b01;
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assign hold_data[0:31] = (prio_alu_out_vld) ? alu_result[32:63] : 32'b0;
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assign out_resp1[0:1] = (hold_id[0:1] == 2'b00) ? hold_resp[0:1] : 2'b00;
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assign out_resp2[0:1] = (hold_id[0:1] == 2'b01) ? hold_resp[0:1] : 2'b00;
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assign out_resp3[0:1] = (hold_id[0:1] == 2'b10) ? hold_resp[0:1] : 2'b00;
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assign out_resp4[0:1] = (hold_id[0:1] == 2'b11) ? hold_resp[0:1] : 2'b00;
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assign out_data1[0:31] = (hold_id[0:1] == 2'b00) ? hold_data[0:31] : 32'b0;
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assign out_data2[0:31] = (hold_id[0:1] == 2'b01) ? hold_data[0:31] : 32'b0;
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assign out_data3[0:31] = (hold_id[0:1] == 2'b10) ? hold_data[0:31] : 32'b0;
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assign out_data4[0:31] = (hold_id[0:1] == 2'b11) ? hold_data[0:31] : 32'b0;
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endmodule
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278
code/vezba6_7/dut/calc_top.v
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278
code/vezba6_7/dut/calc_top.v
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@@ -0,0 +1,278 @@
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// Library: calc1
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// Module: Top-level wiring
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// Author: Naseer Siddique
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//`include "alu_input_stage.v"
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//`include "alu_output_stage.v"
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//`include "exdbin_mac.v"
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//`include "holdreg.v"
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//`include "mux_out.v"
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//`include "shifter.v"
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//`include "priority.v"
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module calc_top (out_data1, out_data2, out_data3, out_data4, out_resp1, out_resp2, out_resp3, out_resp4, c_clk, req1_cmd_in, req1_data_in, req2_cmd_in, req2_data_in, req3_cmd_in, req3_data_in, req4_cmd_in, req4_data_in, reset);
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output [0:31] out_data1,
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out_data2,
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out_data3,
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out_data4;
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output [0:1] out_resp1,
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out_resp2,
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out_resp3,
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out_resp4;
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input c_clk;
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input [0:3] req1_cmd_in,
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req2_cmd_in,
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req3_cmd_in,
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req4_cmd_in;
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input [0:31] req1_data_in,
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req2_data_in,
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req3_data_in,
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req4_data_in;
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input [1:7] reset;
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wire [0:63] add_sum,
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fxu_areg_q,
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fxu_breg_q,
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shift_out,
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shift_places,
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shift_val;
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wire [0:31] hold1_data1,
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hold1_data2,
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hold2_data1,
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hold2_data2,
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hold3_data1,
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hold3_data2,
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hold4_data1,
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hold4_data2,
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mux1_req_data1,
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mux1_req_data2,
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mux2_req_data1,
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mux2_req_data2,
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mux3_req_data1,
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mux3_req_data2,
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mux4_req_data1,
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mux4_req_data2;
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wire [0:3] hold1_prio_req,
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hold2_prio_req,
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hold3_prio_req,
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hold4_prio_req,
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prio_alu1_in_cmd,
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prio_alu2_in_cmd;
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wire [0:1] mux1_req_resp1,
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mux1_req_resp2,
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mux2_req_resp1,
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mux2_req_resp2,
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mux3_req_resp1,
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mux3_req_resp2,
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mux4_req_resp1,
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mux4_req_resp2,
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prio_alu1_in_req_id,
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prio_alu1_out_req_id,
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prio_alu2_in_req_id,
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prio_alu2_out_req_id;
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wire prio_alu1_out_vld,
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prio_alu2_out_vld,
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add_ovfl,
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shift_ovfl;
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wire [0:3] error_found;
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assign error_found = 4'b0000;
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exdbin_mac adder (
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.alu_cmd ( prio_alu1_in_cmd[0:3] ),
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.bin_ovfl ( add_ovfl ),
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.bin_sum ( add_sum[0:63] ),
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.fxu_areg_q ( fxu_areg_q[0:63] ),
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.fxu_breg_q ( fxu_breg_q[0:63] ),
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.local_error_found ( error_found[0] )
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);
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holdreg holdreg1(
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.c_clk ( c_clk ),
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.hold_data1 ( hold1_data1[0:31] ),
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.hold_data2 ( hold1_data2[0:31] ),
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.hold_prio_req ( hold1_prio_req[0:3] ),
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.req_cmd_in ( req1_cmd_in[0:3] ),
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.req_data_in ( req1_data_in[0:31] ),
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.reset ( reset [1: 7] )
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);
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holdreg holdreg2(
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.c_clk ( c_clk ),
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.hold_data1 ( hold2_data1[0:31] ),
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.hold_data2 ( hold2_data2[0:31] ),
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.hold_prio_req ( hold2_prio_req[0:3] ),
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.req_cmd_in ( req2_cmd_in[0:3] ),
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.req_data_in ( req2_data_in[0:31] ),
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.reset ( reset [1: 7] )
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);
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holdreg holdreg3(
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.c_clk ( c_clk ),
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.hold_data1 ( hold3_data1[0:31] ),
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.hold_data2 ( hold3_data2[0:31] ),
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.hold_prio_req ( hold3_prio_req[0:3] ),
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.req_cmd_in ( req3_cmd_in[0:3] ),
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.req_data_in ( req3_data_in[0:31] ),
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.reset ( reset [1: 7] )
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);
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holdreg holdreg4(
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.c_clk ( c_clk ),
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.hold_data1 ( hold4_data1[0:31] ),
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.hold_data2 ( hold4_data2[0:31] ),
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.hold_prio_req ( hold4_prio_req[0:3] ),
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.req_cmd_in ( req4_cmd_in[0:3] ),
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.req_data_in ( req4_data_in[0:31] ),
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.reset ( reset [1: 7] )
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);
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alu_input_stage in_stage1(
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.alu_data1 ( fxu_areg_q[0:63]),
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.alu_data2 ( fxu_breg_q[0:63]),
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.hold1_data1 ( hold1_data1[0:31]),
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.hold1_data2 ( hold1_data2[0:31]),
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.hold2_data1 ( hold2_data1[0:31]),
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.hold2_data2 ( hold2_data2[0:31]),
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.hold3_data1 ( hold3_data1[0:31]),
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.hold3_data2 ( hold3_data2[0:31]),
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.hold4_data1 ( hold4_data1[0:31]),
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.hold4_data2 ( hold4_data2[0:31]),
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.prio_alu_in_cmd ( prio_alu1_in_cmd[0:3]),
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.prio_alu_in_req_id ( prio_alu1_in_req_id[0:1])
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);
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alu_input_stage in_stage2(
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.alu_data1 ( shift_val[0:63]),
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.alu_data2 ( shift_places[0:63]),
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.hold1_data1 ( hold1_data1[0:31]),
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.hold1_data2 ( hold1_data2[0:31]),
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.hold2_data1 ( hold2_data1[0:31]),
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.hold2_data2 ( hold2_data2[0:31]),
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.hold3_data1 ( hold3_data1[0:31]),
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.hold3_data2 ( hold3_data2[0:31]),
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.hold4_data1 ( hold4_data1[0:31]),
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.hold4_data2 ( hold4_data2[0:31]),
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.prio_alu_in_cmd ( prio_alu2_in_cmd[0:3]),
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.prio_alu_in_req_id ( prio_alu2_in_req_id[0:1])
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);
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mux_out mux_out1(
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.req_data1 ( mux1_req_data1[0:31]),
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.req_data2 ( mux1_req_data2[0:31]),
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.req_data ( out_data1[0:31]),
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.req_resp1 ( mux1_req_resp1[0:1]),
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.req_resp2 ( mux1_req_resp2[0:1]),
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.req_resp ( out_resp1[0:1])
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);
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mux_out mux_out2(
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.req_data1 ( mux2_req_data1[0:31]),
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.req_data2 ( mux2_req_data2[0:31]),
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.req_data ( out_data2[0:31]),
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.req_resp1 ( mux2_req_resp1[0:1]),
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.req_resp2 ( mux2_req_resp2[0:1]),
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.req_resp ( out_resp2[0:1])
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);
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mux_out mux_out3(
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.req_data1 ( mux3_req_data1[0:31]),
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.req_data2 ( mux3_req_data2[0:31]),
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.req_data ( out_data3[0:31]),
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.req_resp1 ( mux3_req_resp1[0:1]),
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.req_resp2 ( mux3_req_resp2[0:1]),
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.req_resp ( out_resp3[0:1])
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);
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mux_out mux_out4(
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.req_data1 ( mux4_req_data1[0:31]),
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.req_data2 ( mux4_req_data2[0:31]),
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.req_data ( out_data4[0:31]),
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.req_resp1 ( mux4_req_resp1[0:1]),
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.req_resp2 ( mux4_req_resp2[0:1]),
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.req_resp ( out_resp4[0:1])
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);
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alu_output_stage out_stage1(
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.alu_overflow ( add_ovfl),
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.alu_result ( add_sum[0:63]),
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.c_clk ( c_clk),
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.local_error_found ( error_found[2]),
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.out_data1 ( mux1_req_data1[0:31]),
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.out_data2 ( mux2_req_data1[0:31]),
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.out_data3 ( mux3_req_data1[0:31]),
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.out_data4 ( mux4_req_data1[0:31]),
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.out_resp1 ( mux1_req_resp1[0:1]),
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.out_resp2 ( mux2_req_resp1[0:1]),
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.out_resp3 ( mux3_req_resp1[0:1]),
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.out_resp4 ( mux4_req_resp1[0:1]),
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.prio_alu_out_req_id ( prio_alu1_out_req_id[0:1]),
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.prio_alu_out_vld ( prio_alu1_out_vld ),
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.reset ( reset[1:7])
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);
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alu_output_stage out_stage2(
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.alu_overflow ( shift_ovfl),
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.alu_result ( shift_out[0:63]),
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.c_clk ( c_clk),
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.local_error_found ( error_found[2]),
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.out_data1 ( mux1_req_data2[0:31]),
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.out_data2 ( mux2_req_data2[0:31]),
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.out_data3 ( mux3_req_data2[0:31]),
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.out_data4 ( mux4_req_data2[0:31]),
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.out_resp1 ( mux1_req_resp2[0:1]),
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.out_resp2 ( mux2_req_resp2[0:1]),
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.out_resp3 ( mux3_req_resp2[0:1]),
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.out_resp4 ( mux4_req_resp2[0:1]),
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.prio_alu_out_req_id ( prio_alu2_out_req_id[0:1]),
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||||
.prio_alu_out_vld ( prio_alu2_out_vld ),
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.reset ( reset[1:7])
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);
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priority1 priority_logic (
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.c_clk ( c_clk),
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.hold1_prio_req ( hold1_prio_req[0:3]),
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||||
.hold2_prio_req ( hold2_prio_req[0:3]),
|
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.hold3_prio_req ( hold3_prio_req[0:3]),
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.hold4_prio_req ( hold4_prio_req[0:3]),
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.local_error_found ( error_found[3]),
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.prio_alu1_in_cmd ( prio_alu1_in_cmd[0:3]),
|
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.prio_alu1_in_req_id ( prio_alu1_in_req_id[0:1]),
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.prio_alu1_out_req_id ( prio_alu1_out_req_id[0:1]),
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.prio_alu1_out_vld ( prio_alu1_out_vld),
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.prio_alu2_in_cmd ( prio_alu2_in_cmd[0:3]),
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.prio_alu2_in_req_id ( prio_alu2_in_req_id[0:1]),
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.prio_alu2_out_req_id ( prio_alu2_out_req_id[0:1]),
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.prio_alu2_out_vld ( prio_alu2_out_vld),
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.reset ( reset[1:7])
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);
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shifter shifter1(
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.bin_ovfl ( shift_ovfl),
|
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.local_error_found ( error_found[1]),
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.shift_cmd ( prio_alu2_in_cmd[0:3]),
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.shift_out ( shift_out[0:63]),
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.shift_places ( shift_places[0:63]),
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.shift_val ( shift_val[0:63])
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);
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endmodule // calc1_top
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|
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||||
|
||||
|
||||
|
||||
|
||||
|
||||
1279
code/vezba6_7/dut/exdbin_mac.v
Normal file
1279
code/vezba6_7/dut/exdbin_mac.v
Normal file
File diff suppressed because it is too large
Load Diff
56
code/vezba6_7/dut/holdreg.v
Normal file
56
code/vezba6_7/dut/holdreg.v
Normal file
@@ -0,0 +1,56 @@
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// Library: calc1
|
||||
// Module: Hold Register
|
||||
// Author: Naseer Siddique
|
||||
|
||||
module holdreg(hold_data1, hold_data2, hold_prio_req, c_clk, req_cmd_in, req_data_in, reset);
|
||||
|
||||
input c_clk;
|
||||
input [0:3] req_cmd_in;
|
||||
input [1:7] reset;
|
||||
input [0:31] req_data_in;
|
||||
|
||||
output [0:3] hold_prio_req;
|
||||
output [0:31] hold_data1, hold_data2;
|
||||
|
||||
|
||||
reg [0:3] cmd_hold, hold_prio_reg;
|
||||
wire [0:3] cmd_hold_q;
|
||||
reg [0:31] hold_data1_q, hold_data2_q;
|
||||
|
||||
always
|
||||
@ (posedge c_clk) begin
|
||||
fork
|
||||
|
||||
cmd_hold[0:3] <= (reset[1] == 1) ? 4'b0 : req_cmd_in[0:3];
|
||||
hold_prio_reg[0:3] <= cmd_hold[0:3];
|
||||
|
||||
join
|
||||
|
||||
end
|
||||
|
||||
|
||||
always
|
||||
@ (posedge c_clk) begin
|
||||
fork
|
||||
hold_data1_q[0:31] <=
|
||||
(reset[1]) ? 32'b0 :
|
||||
(req_cmd_in[0:3] != 4'b0) ? req_data_in[0:31] :
|
||||
hold_data1_q[0:31];
|
||||
|
||||
hold_data2_q[0:31] <=
|
||||
(reset[1]) ? 32'b0 : (cmd_hold[0:3] != 4'b0) ?
|
||||
req_data_in[0:31] : hold_data2_q[0:31];
|
||||
join
|
||||
|
||||
end
|
||||
|
||||
|
||||
assign hold_data1 = hold_data1_q;
|
||||
assign hold_data2 = hold_data2_q;
|
||||
assign hold_prio_req = hold_prio_reg;
|
||||
|
||||
endmodule // holdreg
|
||||
|
||||
|
||||
|
||||
|
||||
27
code/vezba6_7/dut/mux_out.v
Normal file
27
code/vezba6_7/dut/mux_out.v
Normal file
@@ -0,0 +1,27 @@
|
||||
// Library: calc1
|
||||
// Module: Output Mux
|
||||
// Author: Naseer Siddique
|
||||
|
||||
module mux_out(req_data, req_resp, req_data1, req_data2, req_resp1, req_resp2);
|
||||
|
||||
output [0:31] req_data;
|
||||
output [0:1] req_resp;
|
||||
|
||||
input [0:31] req_data1, req_data2;
|
||||
input [0:1] req_resp1, req_resp2;
|
||||
|
||||
assign req_resp[0:1] =
|
||||
(req_resp1[0:1] != 2'b00) ? req_resp1 :
|
||||
( req_resp2[0:1] != 2'b00 ) ? req_resp2 :
|
||||
2'b00;
|
||||
|
||||
assign req_data[0:31] =
|
||||
( req_resp1[0:1] != 2'b00 ) ? req_data1 :
|
||||
( req_resp2[0:1] != 2'b00 ) ? req_data2 :
|
||||
32'b0;
|
||||
|
||||
|
||||
|
||||
endmodule // mux_out
|
||||
|
||||
|
||||
155
code/vezba6_7/dut/priority.v
Normal file
155
code/vezba6_7/dut/priority.v
Normal file
@@ -0,0 +1,155 @@
|
||||
// Library: calc1
|
||||
// Priority Logic
|
||||
// Author: Naseer Siddique
|
||||
module priority1 ( prio_alu1_in_cmd, prio_alu1_in_req_id, prio_alu1_out_req_id, prio_alu1_out_vld, prio_alu2_in_cmd, prio_alu2_in_req_id, prio_alu2_out_req_id, prio_alu2_out_vld, c_clk, hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req, local_error_found, reset);
|
||||
|
||||
|
||||
output [0:3] prio_alu1_in_cmd, prio_alu2_in_cmd;
|
||||
output [0:1] prio_alu1_out_req_id, prio_alu1_in_req_id, prio_alu2_in_req_id, prio_alu2_out_req_id;
|
||||
output prio_alu1_out_vld, prio_alu2_out_vld;
|
||||
|
||||
input c_clk, local_error_found;
|
||||
input [0:3] hold1_prio_req, hold2_prio_req, hold3_prio_req, hold4_prio_req;
|
||||
input [1:7] reset;
|
||||
|
||||
reg [0:3] cmd1, cmd2, cmd3, cmd4;
|
||||
reg delay1, delay2;
|
||||
|
||||
wire cmd1_reset, cmd2_reset, cmd3_reset, cmd4_reset;
|
||||
|
||||
reg [0:1] prio_req1_id_q, prio_req2_id_q;
|
||||
|
||||
reg prio_alu1_out_vld_q, prio_alu2_out_vld_q;
|
||||
|
||||
always
|
||||
@ (posedge c_clk) begin
|
||||
if (reset[1]) begin
|
||||
cmd1 <= 0;
|
||||
cmd2 <= 0;
|
||||
cmd3 <= 0;
|
||||
cmd4 <= 0;
|
||||
end
|
||||
else begin
|
||||
fork
|
||||
delay1 <= prio_alu1_out_vld_q;
|
||||
delay2 <= prio_alu2_out_vld_q;
|
||||
|
||||
cmd1[0:3] <=
|
||||
(hold1_prio_req[0:3] != 4'b0) ? hold1_prio_req[0:3] :
|
||||
(cmd1_reset) ? 4'b0 :
|
||||
cmd1[0:3];
|
||||
|
||||
cmd2[0:3] <=
|
||||
(hold2_prio_req[0:3] != 4'b0) ? hold2_prio_req[0:3] :
|
||||
(cmd2_reset) ? 4'b0 :
|
||||
cmd2[0:3];
|
||||
|
||||
cmd3[0:3] <=
|
||||
(hold3_prio_req[0:3] != 4'b0) ? hold3_prio_req[0:3] :
|
||||
(cmd3_reset) ? 4'b0 :
|
||||
cmd3[0:3];
|
||||
|
||||
cmd4[0:3] <=
|
||||
(hold4_prio_req[0:3] != 4'b0) ? hold4_prio_req[0:3] :
|
||||
(cmd4_reset) ? 4'b0 :
|
||||
cmd4[0:3];
|
||||
join
|
||||
end
|
||||
|
||||
|
||||
end // always @ (posedge c_clk)
|
||||
|
||||
always
|
||||
@ (delay1 or delay2 or cmd1 or cmd2 or cmd3 or cmd4) begin
|
||||
|
||||
if (delay1)
|
||||
prio_alu1_out_vld_q <= 1'b0;
|
||||
else if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
|
||||
prio_alu1_out_vld_q <= 1'b1;
|
||||
else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
|
||||
prio_alu1_out_vld_q <= 1'b1;
|
||||
else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
|
||||
prio_alu1_out_vld_q <= 1'b1;
|
||||
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) && local_error_found )
|
||||
prio_alu1_out_vld_q <= 1'b1;
|
||||
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
|
||||
prio_alu1_out_vld_q <= 1'b0;
|
||||
else prio_alu1_out_vld_q <= 1'b0;
|
||||
|
||||
if (delay2)
|
||||
prio_alu2_out_vld_q <= 1'b0;
|
||||
else if (cmd1 > 4'b0011)
|
||||
prio_alu2_out_vld_q <= 1'b1;
|
||||
else if (cmd2 > 4'b0011)
|
||||
prio_alu2_out_vld_q <= 1'b1;
|
||||
else if (cmd3 > 4'b0011)
|
||||
prio_alu2_out_vld_q <= 1'b1;
|
||||
else if (cmd4 > 4'b0011)
|
||||
prio_alu2_out_vld_q <= 1'b1;
|
||||
else prio_alu2_out_vld_q <= 1'b0;
|
||||
|
||||
if ( (cmd1 != 4'b0000) && (cmd1 < 4'b0100) )
|
||||
prio_req1_id_q[0:1] <= 2'b00;
|
||||
else if ( (cmd2 != 4'b0000) && (cmd2 < 4'b0100) )
|
||||
prio_req1_id_q[0:1] <= 2'b01;
|
||||
else if ( (cmd3 != 4'b0000) && (cmd3 < 4'b0100) )
|
||||
prio_req1_id_q[0:1] <= 2'b10;
|
||||
else if ( (cmd4 != 4'b0000) && (cmd4 < 4'b0100) )
|
||||
prio_req1_id_q[0:1] <= 2'b11;
|
||||
else prio_req1_id_q[0:1] <= 2'b00;
|
||||
|
||||
if ( cmd1 > 4'b0011 )
|
||||
prio_req2_id_q <= 2'b00;
|
||||
else if ( cmd2 > 4'b0011 )
|
||||
prio_req2_id_q <= 2'b01;
|
||||
else if ( cmd3 > 4'b0011 )
|
||||
prio_req2_id_q <= 2'b10;
|
||||
else if ( cmd4 > 4'b0011 )
|
||||
prio_req2_id_q <= 2'b11;
|
||||
else prio_req2_id_q <= 2'b00;
|
||||
|
||||
end // always @ (delay1 or or delay2 or cmd1 or cmd2 or cmd3 or cmd4)
|
||||
|
||||
assign prio_alu1_in_req_id[0:1] = prio_req1_id_q[0:1];
|
||||
assign prio_alu2_in_req_id[0:1] = prio_req2_id_q[0:1];
|
||||
assign prio_alu1_out_req_id[0:1] = prio_req1_id_q[0:1];
|
||||
assign prio_alu2_out_req_id[0:1] = prio_req2_id_q[0:1];
|
||||
assign prio_alu1_out_vld = prio_alu1_out_vld_q;
|
||||
assign prio_alu2_out_vld = prio_alu2_out_vld_q;
|
||||
|
||||
assign prio_alu1_in_cmd[0:3] =
|
||||
(prio_req1_id_q[0:1] == 2'b00) ? cmd1[0:3] :
|
||||
(prio_req1_id_q[0:1] == 2'b01) ? cmd2[0:3] :
|
||||
(prio_req1_id_q[0:1] == 2'b10) ? cmd3[0:3] :
|
||||
(prio_req1_id_q[0:1] == 2'b11) ? cmd4[0:3] :
|
||||
4'b0;
|
||||
|
||||
assign prio_alu2_in_cmd[0:3] =
|
||||
(prio_req2_id_q[0:1] == 2'b00) ? cmd1[0:3] :
|
||||
(prio_req2_id_q[0:1] == 2'b01) ? cmd2[0:3] :
|
||||
(prio_req2_id_q[0:1] == 2'b10) ? cmd3[0:3] :
|
||||
(prio_req2_id_q[0:1] == 2'b11) ? cmd4[0:3] :
|
||||
4'b0;
|
||||
|
||||
|
||||
assign cmd1_reset =
|
||||
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b00) ) ? 1 :
|
||||
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b00) ) ? 1 :
|
||||
0;
|
||||
|
||||
assign cmd2_reset =
|
||||
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b01) ) ? 1 :
|
||||
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b01) ) ? 1 :
|
||||
0;
|
||||
|
||||
assign cmd3_reset =
|
||||
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b10) ) ? 1 :
|
||||
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b10) ) ? 1 :
|
||||
0;
|
||||
|
||||
assign cmd4_reset =
|
||||
(prio_alu1_out_vld_q && (prio_req1_id_q[0:1] == 2'b11) ) ? 1 :
|
||||
(prio_alu2_out_vld_q && (prio_req2_id_q[0:1] == 2'b11) ) ? 1 :
|
||||
0;
|
||||
|
||||
endmodule // priority
|
||||
2310
code/vezba6_7/dut/shifter.v
Normal file
2310
code/vezba6_7/dut/shifter.v
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user